Reduced potential generation circuit operable at low...

Details Reduced potential generation circuit operable at low... Reduced potential generation circuit operable at low...

2002-08-14

2004-09-28

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S543000, C323S316000

Reexamination Certificate

active

06798276

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to power supply circuits and semiconductor devices, and particularly relates to a power supply circuit for generating an internally reduced potential and to a semiconductor device using such a circuit.
2. Description of the Related Art
In semiconductor devices such as DRAMs, the power supply potential that is supplied from the exterior of the device is internally reduced, thereby driving some circuit elements such as memory core elements by the internally reduced potential.
An internally reduced potential generation circuit that generates the reduced potential typically uses a series of resistors to divide the potential supplied from the external power supply, and sets an upper limit and a lower limit that define a range of the generated reduced potential. The internally reduced potential generation circuit employs a current mirror circuit to control its output potential such that it stays between the upper limit and the lower limit.
FIG. 1
is a circuit diagram showing the configuration of a related-art internally reduced potential generation circuit.
The internally reduced potential generation circuit
10
of
FIG. 1
includes PMOS transistors
11
through
14
, NMOS transistors
15
through
18
, NMOS transistors
21
through
24
, PMOS transistors
25
through
27
, an inverter
31
, a PMOS transistor
32
, an NMOS transistor
33
, and resistors R
1
through R
3
.
The resistors R
1
through R
3
are connected in series, thereby forming a potential divider that divides the potential between a potential VF and a potential VSS. The potential VF is generated from an external power supply potential VDD, and is a fixed potential independent of VDD. The potential divider generates a lower-limit reference potential vl as a lower limit of the reduced potential and an upper-limit reference potential vu as an upper limit of the reduced potential.
The PMOS transistors
11
through
14
and the NMOS transistors
15
through
18
together constitute an NMOS-type current mirror circuit that functions as a comparator. The NMOS-type current mirror circuit has an input node that is the gate of the NMOS transistor
15
, which receives the lower-limit reference potential vl from the potential divider. The NMOS transistors
21
through
24
and the PMOS transistors
25
through
27
together constitute a PMOS-type current mirror circuit that serves as a comparator. The gate of the PMOS transistor
25
serves as the input node of the PMOS-type current mirror circuit, and receives the upper-limit reference potential vu from the potential divider.
The NMOS-type current mirror circuit on the lower-limit side produces an output that is supplied to the gate of the PMOS transistor
32
. The output of the PMOS-type current mirror circuit on the upper-limit side is supplied to the gate of the NMOS transistor
33
. The PMOS transistor
32
and the NMOS transistor
33
are connected with each other at their drains, and a reduced potential vp is output from the joint point between these transistors. The generated reduced potential vpr is supplied to internal circuitry of the semiconductor device, and is also fed back to the NMOS-type current mirror circuit on the lower-limit side and the PMOS-type current mirror circuit on the upper-limit side.
The NMOS-type current mirror circuit on the lower-limit side compares the generated reduced potential vpr with the lower-limit reference potential vl. If the reduced potential vpr is below the lower-limit reference potential vl, the NMOS transistor
15
becomes conductive to pull down the potential of a node n
0
to LOW. This results in the PMOS transistor
32
being conductive to pull up the reduced potential vpr. If the reduced potential vpr is above the lower-limit reference potential vl, the NMOS transistor
15
becomes nonconductive so as to keep the potential of the node n
0
at HIGH, thereby making the PMOS transistor
32
nonconductive.
The PMOS-type current mirror circuit on the upper-limit side compares the generated reduced potential vpr with the upper-limit reference potential vu. If the reduced potential vpr is above the upper-limit reference potential vu, the PMOS transistor
25
becomes conductive to pull up the potential of a node n
1
to HIGH. This results in the NMOS transistor
33
being conductive to pull down the reduced potential vpr. If the reduced potential vpr is below the upper-limit reference potential vu, the PMOS transistor
25
becomes nonconductive so as to keep the potential of the node n
1
at LOW, thereby making the NMOS transistor
33
nonconductive.
A signal ulp becomes HIGH when the semiconductor device is set in the low power consumption mode. When the low-power-consumption-mode entry signal ulp turns to HIGH, the NMOS transistors
21
and
24
become conductive, and PMOS transistor
27
become nonconductive. As a result, the PMOS-type current mirror circuit on the upper-limit side stops operating. The potential at the node n
1
is changed to LOW, which makes the NMOS transistor
33
nonconductive. This prevents a leak current from running from the reduced potential vpr to the ground potential VSS. By the same token, the PMOS transistors
11
and
14
are turned on, and the NMOS transistor
18
is turned off. This changes the potential at the node n
0
to HIGH, thereby making the PMOS transistor
32
nonconductive.
By operating as described above, the internally reduced potential generation circuit
10
produces and controls the reduced potential vpr such that the reduced potential vpr falls between the upper-limit reference potential vu and the lower-limit reference potential vl.
Semiconductor devices of today are often provided with an external power supply potential that is set relatively low with an aim of reducing power consumption. The internally reduced potential generation circuit
10
of
FIG. 1
uses the PMOS-type current mirror circuit on the upper-limit side. When the external power supply potential VDD is lowered, the difference between the upper-limit reference potential vu and the power supply potential VDD becomes small, resulting in the PMOS transistors
25
and
26
being not fully conductive. As a result, the PMOS-type current mirror circuit on the upper-limit side may not be able to exhibit a sufficient gain.
Accordingly, there is a need for a power supply circuit and a semiconductor device which can properly generate an internally reduce potential even when the external power supply potential is relatively low.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a power supply circuit and a semiconductor device that substantially obviate one or more of the problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be set forth in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a power supply circuit and a semiconductor device particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a power supply circuit according to the present invention includes a first NMOS-type current mirror circuit which compares a first potential with a second potential, a second NMOS-type current mirror circuit which compares the first potential with a third potential, and a potential setting circuit which adjusts the first potential in response to outputs of the first and second NMOS-type current mirror circuits, such that the first potential falls between the second potential and the third potential.
In the power supply c

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