Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-12-31
2004-09-21
Nhu, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S230040
Reexamination Certificate
active
06795345
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device having a virtual ground-type memory cell array.
2. Description of the Background Art
In an EEPROM (Electrically Erasable Programmable Read-Only Memory) one side of a memory transistor is, in general, connected to a source line coupled to the ground potential and it is necessary to provide source lines at predetermined intervals between bit lines and, therefore, an increase in integration density is difficult. Therefore, research concerning virtual ground-type memory cell arrays has been carried out in recent years. A virtual ground-type memory cell array (virtual ground array) is disclosed in Japanese Patent Laying-Open No. 9-82921.
In addition, NROM (Nitride Read Only Memory)-type flash EEPROMs (hereinafter referred to as NROM), which are one type of flash EEPROM from among non-volatile semiconductor memory devices, have been obtaining attention. An NROM has an ONO (Oxide Nitride Oxide) film as a gate insulating film so that two bits of information can be stored in one memory cell. Reduction in chip area per bit can be expected in an NROM, in comparison with other non-volatile semiconductor memory devices having floating gates. An NROM is disclosed in U.S. Pat. No. 6,081,456. A virtual ground-type memory cell array is used in the NROM therein.
FIG. 57
is a circuit diagram for describing how a potential is supplied to a bit line in a virtual ground-type memory cell array of a conventional NROM.
With reference to
FIG. 57
, a memory cell array
502
includes bit lines BL
1
to BL
5
, word lines WL
1
to WLn, memory cells
511
to
514
, of which the respective gates are connected to word line WL
1
, and memory cells
521
to
524
, of which the respective gates are connected to word line WLn.
In memory cell array
502
, memory cells adjacent to each other, from among memory cells aligned in a line sharing one word line, share one bit line. That is to say, memory cell
511
and memory cell
512
are connected to bit line BL
2
at a node NB so as to share bit line BL
2
. Memory cell
512
and memory cell
513
are connected to bit line BL
3
at a node NA so as to share bit line BL
3
. Memory cell array
502
is a so-called virtual ground-type memory cell array wherein the bit line that corresponds to the memory cell to be accessed is connected to the ground potential.
A switching circuit
504
is provided in order to selectively supply a desired potential to a bit line of memory cell array
502
. Switching circuit
504
includes switching parts
531
to
535
provided corresponding to bit lines BL
1
to BL
5
, respectively.
Switching part
531
includes an N-channel MOS transistor
542
, of which the gate receives a control signal VG
1
, connected between a reading power supply line
524
, to which a reading power supply potential VddR is supplied via a sense amplifier circuit
501
, and bit line BL
1
, and an N-channel MOS transistor
544
, of which the gate receives a control signal GG
1
, connected between a ground power supply line
522
, to which power potential GND is supplied, and bit line BL
1
.
Switching part
532
includes an N-channel MOS transistor
552
, of which the gate receives a control signal VG
2
, connected between reading power supply line
524
and bit line BL
2
, and an N-channel MOS transistor
554
, of which the gate receives a control signal GG
2
, connected between ground power supply line
522
and bit line BL
2
.
Switching part
533
includes an N-channel MOS transistor
562
, of which the gate receives a control signal VG
3
, connected between reading power supply line
524
and bit line BL
3
, and an N-channel MOS transistor
564
, of which the gate receives a control signal GG
3
, connected between ground power supply line
522
and bit line BL
3
.
Switching part
534
includes an N-channel MOS transistor
572
, of which the gate receives a control signal VG
4
, connected between reading power supply line
524
and bit line BL
4
, and an N-channel MOS transistor
574
, of which the gate receives a control signal GG
4
, connected between ground power supply line
522
and bit line BL
4
.
Switching part
535
includes an N-channel MOS transistor
582
, of which the gate receives a control signal VG
5
, connected between reading power supply line
524
and bit line BL
5
, and an N-channel MOS transistor
584
, of which the gate receives a control signal GG
5
, connected between ground power supply line
522
and bit line BL
5
.
Reading of data from the memory cell array is carried out by a current detection-type sense amplifier
501
.
FIG. 58
is a cross sectional view for describing a cross sectional structure of memory cell
512
in FIG.
57
.
With reference to
FIG. 58
, n-type impurity regions
202
and
204
are formed in a P-type substrate
200
. These n-type impurity regions
202
and
204
, respectively, correspond to bit lines BL
2
and BL
3
of FIG.
57
. Bit lines BL
2
and BL
3
are buried-type bit lines and have a high resistance.
Silicon oxide films
206
and
208
for element isolation, respectively, are formed above n-type impurity regions
202
and
204
. A silicon oxide film
210
is formed on top of a region between n-type impurity region
202
and n-type impurity region
204
, and, in addition, a nitride film
212
for storing a charge is formed on top of silicon oxide film
210
and, furthermore, a silicon oxide film
214
is formed on top of nitride film
212
. Such a three-layer gate insulating film is referred to as an ONO (Oxide Nitride Oxide) layered structure.
A conductive layer
216
, formed of polycrystalline silicon or the like, is formed over silicon oxide films
206
,
214
and
208
. Conductive layer
216
corresponds to word line WL
1
of FIG.
57
.
Here, other memory cells of
FIG. 57
have the same structure as memory cell
512
and, therefore, descriptions thereof will not be repeated.
As shown in the cross sectional view of
FIG. 58
, a memory cell is formed of one field effect transistor. One bit of information can be stored in a region L
1
in the left side of nitride film
212
and another one bit can be stored in a region L
2
in the right side of nitride film
212
.
Next, programming and reading of data to and from a memory cell will be described. In the memory cell array shown in
FIG. 57
, each of two bit lines between which memory cells are placed is connectable to either ground power supply line
522
or reading power supply line
524
. In such a configuration, the direction of voltage applied to the memory cells can freely be changed. Each memory cell has two memory regions so that programming and reading of data can be carried out to and from different memory regions by changing the direction in which current flows. In the following description, memory cell
512
is focused on as a representative memory cell.
FIG. 59
is a diagram for describing the programming operation of data to memory region L
1
of memory cell
512
.
With reference to
FIG. 59
, in the case that data written in to memory region L
1
, the potential of bit line BL
2
is set at programming potential VddW and the potential of bit line BL
3
is set at power potential GND. When word line WL
1
is activated to the H level for the programming condition, a programming current Iw
1
flows from bit line BL
2
through non-volatile memory cell
512
toward bit line BL
3
. At this time, data is written in to memory region L
1
.
FIG. 60
is a diagram for describing the reading operation of data from memory region L
1
of memory cell
512
.
With reference to
FIG. 60
, in the case that data is reading from memory region L
1
, a reading power supply potential VddR is supplied to bit line BL
3
via current detection-type sense amplifier circuit
501
. In addition, bit line BL
2
is coupled to ground potential GND. In the case wherein the potential of the bit line is set in such a manner, the threshold voltage value of the memory cell becomes greater wh
Nhu David
Renesas Technology Corp.
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