Coarse tuning for fractional-N synthesizers

Details Coarse tuning for fractional-N synthesizers Coarse tuning for fractional-N synthesizers

2002-04-22

2004-03-23

Shingleton, Michael B (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

C331S017000, C331S025000

Reexamination Certificate

active

06710664

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates in general to fractional-N synthesizers, and, in particular, to a technique to provide coarse tuning of an oscillator in a fractional-N synthesizer.
BACKGROUND OF THE INVENTION
Frequency synthesizers are used in many systems, including microprocessors and radio frequency (RF) communication systems. Frequency synthesizers of the phase locked loop (PLL) type contain controlled oscillators (CO) that are typically current controlled oscillators (ICO) or voltage controlled oscillators (VCO). The output of the CO is often used as an injection signal for an RF mixer or in a microprocessor clock system. The frequency synthesizer controls the CO such that its frequency or period is approximately equal to that of a stable frequency reference multiplied by a predetermined ratio. In many applications, there is a need to compensate for process and environmental variations that affect synthesizer performance. The prior art contains many systems that compensate for variations in the CO's frequency tuning range or center frequency by performing a coarse tuning of the tunable elements in the CO. These systems have been developed for integer-N synthesizers where the divided CO signal used for feedback to the phase detector has a steady period when the CO's output frequency is not changing.
The use of fractional-N synthesizers provides reduced lock times for the synthesizer's phase lock loop (PLL) and improves noise performance, but introduces significant jitter on the divided CO signal. Even with a constant CO output frequency, the divider modulus is constantly changing to provide a desired average fractional modulus over a period of time. The jitter on the divided CO signal significantly reduces the accuracy of existing techniques for calibrating and tuning the CO. Accordingly, there is a need for a technique to reduce the impact of jitter on the divided CO signal and provide accurate calibration or coarse tuning of a CO in a fractional-N synthesizer in a cost-effective and efficient manner.
SUMMARY OF THE INVENTION
The present invention provides an efficient coarse tuning process for fractional-N synthesizers. In general, a reference signal and a divided controllable oscillator (CO) signal from the phase lock loop (PLL) of a synthesizer are each further divided by a common factor M to provide an average reference signal and an average CO signal, respectively. Frequency division by a factor M is an efficient method of adding the durations of M successive periods of the divided CO signal. The period of the average CO signal is approximately equal to M times the average period of the divided CO signal. When the synthesizer is in lock, the average period of the divided CO signal is approximately equal to the period of the reference signal. Hence, the period of the average CO signal is approximately equal to the period of the average reference signal. Averaging the divided CO signal reduces jitter caused by fractional-N division of the CO signal. The frequencies of the average CO signal and the average reference signal are compared and the result is used to select an appropriate tuning curve for operating the CO.
In one embodiment, the capacitance value of a switched capacitance in the resonant tank or analogous frequency control circuit of the CO is selected based on comparing the frequencies of the average CO and average reference signals. These frequencies may be compared by measuring the periods for the respective signals. Preferably, the process repeats for each tuning curve by progressively incrementing or decrementing the capacitance value of the switched capacitance until an acceptable tuning curve is selected.
Accordingly, a first divider circuit divides the divided reference signal by a factor of M to create an average reference signal. A second divider circuit divides the divided CO signal by a factor of M to create an average CO signal. Tuning logic processes the average reference signal and average CO signal to provide a CO control signal, which controls calibration of the CO. In the preferred embodiment, the tuning logic is a state machine configured to compare the periods of the average CO signal and average reference signal and provide a pulse for the CO control signal to control a coarse tune counter. The output of the coarse tune counter provides a CO tank capacitance-select signal to select a capacitance value of the CO's resonant tank circuit.
During coarse tuning, the CO fine tuning signal is forced to a desired initialization value under the control of the tuning logic. The tuning logic will typically provide a loop filter control signal to cause a switch to apply the initialization value to the fine tuning signal of the CO. The capacitance of the tank capacitance circuit is incremented or decremented throughout a desired operating range until the average CO signal and average reference signal are substantially the same. At this point, the initialization value is removed from the fine tuning signal and the PLL is allowed to lock in traditional fashion.


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Vogelmann et al. “20 mW SiGe-MMIC-VCO at 5 GHz with Integrated 4:1 Divider for Use in a PLL” Silcon Monolithic Integrated Circuits in RF Systems 2001 Sep. 12-14, 2001 pp 222-225.

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