Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2003-03-20
2004-03-30
Nguyen, Khanh Van (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S253000
Reexamination Certificate
active
06714077
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an operational amplifier, and more particularly to an operational amplifier that is composed of MOS transistors and capable of obtaining a relatively large output current with a low voltage.
2. Description of the Related Art
FIG. 2
is a structural diagram showing an example of a conventional operational amplifier.
The operational amplifier is composed of a differential input section
10
that amplifies a differential voltage between two input signals inputted to an inverting or inverse input terminal
1
and to a non-inverting or uninverse input terminal
2
, an amplifying section
20
Z that amplifies an output signal from the differential input section
10
, an output section
30
Z that outputs a signal amplified by the amplifying section
20
Z to an output terminal
3
with a low output impedance, and a bias generating section
40
that generates a bias voltage necessary for the respective sections.
The differential input section
10
includes a p-channel MOS transistor
11
, and a source thereof is connected to a supply voltage VDD. A bias voltage VB
1
is applied to a gate of the p-channel MOS transistor
11
from the bias generating section
40
. A drain of the p-channel MOS transistor
11
is connected with sources of p-channel MOS transistors
12
and
13
, respectively, and gates of those p-channel MOS transistors
12
and
13
are connected to the inverse input terminal
1
and the uninverse input terminal
2
, respectively. The drain of the p-channel MOS transistor
12
is connected to a drain and a gate of an n-channel MOS transistor
14
as well as a gate of an n-channel MOS transistor
15
, respectively. Sources of the n-channel MOS transistors
14
and
15
are grounded to a ground voltage GND. Drains of the p-channel MOS transistor
13
and the n-channel MOS transistor
15
are connected to a node N
1
, respectively, and a signal V
1
is outputted to the node N
1
from the differential input section
10
.
The amplifying section
20
Z includes a p-channel MOS transistor
26
, and the supply voltage VDD is applied to a source of the p-channel MOS transistor
26
. The bias voltage VB
1
is applied to a gate of the p-channel MOS transistor
26
from the bias generating section
40
. A drain of the p-channel MOS transistor
26
is connected to a node N
2
which is connected with sources of an n-channel MOS transistor
27
and a p-channel MOS transistor
28
, respectively. Bias voltages VB
2
and VB
3
are applied to gates of the n-channel MOS transistor
27
and the p-channel MOS transistor
28
from the bias generating section
40
, respectively. Drains of the n-channel MOS transistor
27
and the p-channel MOS transistor
28
are connected to the node N
3
, respectively, and the node N
3
is connected with a drain of an n-channel MOS transistor
29
. A gate of the n-channel MOS transistor
29
is connected to the node N
1
, and a source of the n-channel MOS transistor
29
is grounded to the ground voltage GND.
The output section
30
Z is composed of a p-channel MOS transistor
38
and an n-channel MOS transistor
39
, and a source, a gate and a drain of the p-channel MOS transistor
38
are connected to the supply voltage VDD, the node N
2
and the output terminal
3
, respectively. A drain, a gate and a source of the n-channel MOS transistor
39
are connected to the output terminal
3
, the node N
3
and the ground voltage GND, respectively.
In the operational amplifier thus structured, the differential voltage between an input signal VI
1
supplied to the inverse input terminal
1
and an input signal VI
2
supplied to the uninverse input terminal
2
is amplified by the differential input section
10
and then outputted to the node N
1
as the signal V
1
. The signal V
1
is amplified by the amplifying section
20
Z and then supplied to the gate of the n-channel MOS transistor
39
in the output section
30
Z from the node N
3
. Also, a signal that permits a given output current to flow in the output section
30
Z is supplied to the gate of the PMOS
38
in the output section
30
Z.
With the above structure, the differential voltage between the input signals VI
1
and VI
2
is amplified and an output voltage VO is outputted from the output terminal
3
.
However, the conventional operational amplifier thus structured by the MOS transistors suffers from problems stated below.
FIG. 3
is a graph showing an example of the characteristic of the MOS transistor.
In
FIG. 3
, assuming that the supply voltage VDD is 2 V, a relation of a voltage Vgs between the gate and the source of the n-channel MOS transistor
39
in the output section
30
Z and a drain current Id thereof is represented with the gate width W of the MOS transistor as a parameter. In this example, the gate length L is set to 1 &mgr;m.
As shown in
FIG. 3
, if the voltage Vgs between the gate and the source of the n-channel MOS transistor
39
is held constant, it is necessary to widen the gate width W in order to obtain a large drain current Id. Also, it is apparent from the graph that the larger the voltage Vgs between the gate and the source is, the narrower the gate width necessary for obtaining a given drain current Id.
In order that the operational amplifier structured as shown in
FIG. 2
is operated with a low supply voltage VDD such as 3 V to obtain a large output current such as 200 mA, each of the gate widths W of the p-channel MOS transistor
38
and the n-channel MOS transistor
39
in the output section
30
Z is required to be set to about 3 mm. For that reason, the size of the MOS transistors
38
and
39
in the output section
30
Z becomes extremely large, resulting in such a problem that a pattern area serving as the integrated circuit increases.
SUMMARY OF THE INVENTION
The present invention has been made to solve the problem inherent in the conventional operational amplifier, and therefore an object of the present invention is to provide an operational amplifier which is capable of obtaining a large output current with a relatively small pattern area even if the supply voltage VDD is low.
In order to achieve the above object, according to the present invention, there is provided an operational amplifier comprising: a differential input section for generating a first signal corresponding to a differential voltage between two input signals; an amplifying section for amplifying the first signal in voltage to generate second and third complementary signals; a first MOS transistor connected between a first supply voltage and an output node, a conduction state of the first MOS transistor being controlled in accordance with the second signal; a second MOS transistor connected between a second supply voltage and the output node, a conduction state of the second MOS transistor being controlled in accordance with the third signal; and a step-up section for stepping up the first and second supply voltages to generate a step-up voltage higher than the first and second supply voltages; wherein the amplifying section is driven by the step-up voltage so that an absolute value of the maximum level of the second or third signal becomes larger than the absolute value of the first or second supply voltage.
According to the present invention, the operational amplifier thus structured operates as follows:
In the step-up section, a step-up voltage higher than the first and second supply voltage is generated and applied to the amplifying section. In the amplifying section driven by the step-up voltage, the first signal supplied from the differential input section is amplified in voltage to generate the second and third complementary signals such that the absolute values of the maximum levels of those second and third complementary signals become larger than the absolute value of the first or second supply voltage. The second signal is supplied to the first MOS transistor so as to control the conduction state of the first MOS transistor. On the other hand, the third signal is supplied to the second MOS transistor so as
Nguyen Khanh Van
Oki Electric Industry Co. Ltd.
Volentine & Francos, PLLC
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