Wire bond package with core ring formed over I/O cells

Details Wire bond package with core ring formed over I/O cells Wire bond package with core ring formed over I/O cells

2002-02-20

2004-01-06

Zarabian, Amir (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Wire contact, lead, or bond

C257S774000, C257S776000

Reexamination Certificate

active

06674176

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to methods of manufacturing integrated circuits. More specifically, but without limitation thereto, the present invention relates to methods for reducing the die size in an integrated circuit.
BACKGROUND OF THE INVENTION
In previous wire bond package designs, a core ring is formed in a metal layer over an integrated circuit chip (or die) in an area defined between input/output (I/O) cells arranged along the periphery of the die and standard cells arranged in the center of the die. A core ring is a rectilinearly shaped wire conductor in the wire bond package that surrounds the center of the die. Core rings are generally formed as a pair of parallel wires. Typically, one wire conducts power (VDD) and the other wire conducts ground (VSS). Core rings are used for connecting the standard cells to power and ground by straps that connect the core rings to the edge of the wire bond package and by power meshes that cross over the die between identical core rings on opposite sides of the die.
SUMMARY OF THE INVENTION
In one aspect of the present invention, core rings are formed over the I/O core rings that overlap the I/O cells of an integrated circuit die, thereby reducing the space between the I/O cells and the standard cells, advantageously decreasing the required die size. In one embodiment, a wire bond package includes a first I/O core ring and a second I/O core ring formed in a first metal layer; a pad strap formed in a second metal layer to overlap the second I/O core ring; a via formed between the first metal layer and the second metal layer where the second I/O core ring and the pad strap overlap; a first core ring formed in a third metal layer overlapping the first I/O core ring; a via formed between the first metal layer and the third metal layer where the first I/O core ring and the first core ring overlap outside the pad strap; a first power mesh formed in a fourth metal layer overlapping the first core ring; and a via formed between the third metal layer and the fourth metal layer where the first core ring and the first power mesh overlap.
In another embodiment, method of forming a core ring in a wire bond package includes forming a first I/O core ring and a second I/O core ring in a first metal layer; forming a pad strap in a second metal layer overlapping the second I/O core ring; forming a via between the first metal layer and the second metal layer where the second I/O core ring and the pad strap overlap; forming a first core ring in a third metal layer to overlap the first I/O core ring; forming a via between the first metal layer and the third metal layer where the first I/O core ring and the first core ring overlap outside the pad strap; forming a first power mesh in a fourth metal layer overlapping the first core ring; and forming a via between the third metal layer and the fourth metal layer where the first core ring and the first power mesh overlap.


REFERENCES:
patent: 4920398 (1990-04-01), Yoshio et al.
patent: 5311058 (1994-05-01), Smolley
patent: 5721151 (1998-02-01), Padmanabhan et al.
patent: 6194768 (2001-02-01), Gardner et al.
patent: 6194786 (2001-02-01), Orcutt
patent: 6476497 (2002-11-01), Waldron et al.
patent: 6483714 (2002-11-01), Jones
U.S. patent application entitled “High Density Input Output” filed on Nov. 27, 2001 (pending)US Ser. No. 09/994,567; First named inventor: Anwar Ali.
US 2002/0056857 -Author(s) -Yoshiro Iwasa May 16, 2002 09/984,219 United States Patent Application Publication.

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