Low drop-out voltage regulator having split power device

Details Low drop-out voltage regulator having split power device Low drop-out voltage regulator having split power device

2001-12-18

2004-01-13

Patel, Rajnikant B. (Department: 2838)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C323S280000

Reexamination Certificate

active

06677735

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to voltage regulators and, more particularly, to a low drop-out (LDO) voltage regulator with a split power device.
BACKGROUND OF THE INVENTION
A low drop-out (LDO) regulator is typically used in electronic devices such as cellular phones, laptop computers and other battery-powered electronic devices having a number of requirements relating to voltage regulation. An LDO is a type of linear regulator. A linear regulator uses a transistor or FET, operating in its linear region, to subtract excess voltage from the applied input voltage, producing a regulated output voltage. Dropout voltage is the minimum input to output voltage differential required for the regulator to sustain an output voltage within 100 mV of its nominal value.
LDO regulators for positive output voltages often use a PNP for the power transistor (also called a pass device). This transistor is allowed to saturate, so the regulator can have a very low drop-out voltage, typically around 200 mV compared with around 2 V for traditional linear regulators using an NPN composite power transistor. A negative-output LDO uses an NPN for its pass device, operating in a manner similar to that of the positive-output LDO's PNP device. Newer developments using a CMOS power transistor can provide the lowest drop-out voltage. With CMOS the only voltage drop across the regulator is the ON resistance of the power device times the load current. With light loads this can become just a few tens of millivolts.
An LDO with minimum quiescent current is desirable for battery powered applications. To minimize the quiescent current at light loads, while maintaining good transient performance at heavy loads, it is standard practice to have the LDO work in two modes: “sleep” and “on.” Usually, in “sleep” mode, the maximum load current is limited to a few milliamps and quiescent current is at a minimum (approximately 10-20 &mgr;A). While in “on” mode, the load current can be as much as a few hundred milliamps and the quiescent current is higher (50-100 &mgr;A). A single power device for both operation modes, while satisfying heavy load operation, puts significant challenges on compensation in sleep mode. For example, in an internally compensated PMOS LDO in sleep mode, when the quiescent current is cut down and the parasitic pole at the PMOS gate moves to lower frequencies, a larger Miller capacitor is needed to reduce the bandwidth in order to maintain stability. This requires additional area.
It is therefore desirable to reduce the gate capacitance and simplify the compensation needed to maintain stability, without requiring additional and/or larger Miller capacitors. The present invention provides this by splitting the output of the driver for different operational modes, selectively driving a small power device, a large power device or both based on the mode.


REFERENCES:
patent: 4779037 (1988-10-01), LoCascio
patent: 6469480 (2002-10-01), Kanakubo

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