Integral nonlinearity error correction circuitry and method...

Details Integral nonlinearity error correction circuitry and method... Integral nonlinearity error correction circuitry and method...

2003-04-21

2004-03-16

Young, Brian (Department: 2819)

Coded data generation or conversion

Converter calibration or testing

C341S144000, C341S145000

Reexamination Certificate

active

06707404

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to string digital-to-analog converters (string DACs) and associated interpolation circuits thereof, and more particularly to circuitry and techniques for calibrating interpolating string DACs to correct integral nonlinearity (INL) errors.
The assignee's U.S. Pat. No. 6,246,351 issued Jun. 12, 2001 entitled “LSB Interpolation Circuits and Method for Segmented Digital-to-Analog Converter”, incorporated herein by reference, and U.S. Pat. No. 6,496,133 issued Dec. 17, 2002 entitled “Resistor String Integrated Circuit and Method for Reduced Linearity Error”, both by the present inventor, are generally indicative of the state of the art for interpolating string DACs.
Monotonicity and low INL are usually required in applications in which DACs, including string DACs, are used. The INL error is the difference between the actual output of a DAC and the “ideal” output of the DAC. Resistor mismatches in string DACs cause INL error. String DACs are commonly fabricated using submicron CMOS technologies wherein it is expensive to utilize precision resistors to ensure monotonicity of the DAC, because manufacture of the precision resistors requires expensive laser trimming operations. The matching of the resistors used in the “string” section of a string DAC limits the INL of a string DAC. With careful layout of the string resistors, 10-bit accuracy of the matching of the resistances of the string resistors is possible in the present state-of-to-art CMOS fabrication processes. Therefore, the INL of a 16-bit interpolating string DAC will be at the 64 LSB level. This means the output of the DAC may be as much as 64 LSBs different than what an ideal DAC would produce, which is unacceptably large for some applications.
Next, the structure and operation of a basic conventional interpolating string DAC will be described. Referring to prior art
FIG. 1
, a 4-bit interpolating string DAC
1
includes a 2-bit coarse string DAC
2
, the output of which is interpolated by 2-bit interpolator DAC
6
. The coarse string DAC
2
includes a resistor string
25
including four equal-resistance series-connected resistors R
1
, R
2
, R
3
, and R
4
and tap points
4
-
1
,
2
,
3
, and
4
therebetween. The voltages on nodes
4
-
1
,
2
,
3
,
4
of the resistor string are assumed to be 48, 56, 108, and 128 “voltage units”. Each of the voltage units referred to is equal to the reference voltage divided by the number of string resistors. Typically, the reference voltage is 1.5 volts, 2.5 volts, or 5 volts. Coarse string DAC
2
produces two output levels Vhigh and Vlow which are the voltage of the upper terminal and lower terminal, respectively, of a selected one of the series-connected resistors R
1
-R
4
that constitute the resistor string of coarse string DAC
2
. The resistor referred to is selected in response to the MSB code b
3
b
2
of the digital input provided to string DAC
1
.
The output of coarse string DAC
2
is applied to the input of an interpolation DAC
6
, which interpolates to produce a voltage level that is proportionately between Vhigh and Vlow in response to the LSBs b
1
b
0
of the digital input word applied to string DAC
1
. The structure and operation of string DAC
1
are set forth in detail in above-mentioned U.S. Pat. No. 6,246,351 issued Jun. 12, 2001 entitled “LSB Interpolation Circuits and Method for Segmented Digital-to-Analog Converter”, which is incorporated herein by reference.
The example of prior art
FIG. 1
shows a 2-bit interpolator, but the basic approach can be applied to an n-bit interpolator. Level selection switches
5
operate to connect the input of the interpolator
6
to two consecutive voltages, Vhigh and Vlow. The number of gm stages
8
-
1
,
2
,
3
,
4
having an input connected to Vhigh is equal to the decimal value of the LSB digital input b
1
b
0
that is applied to interpolating switch matrix
7
. In other words, the interpolating switch matrix
7
functions as a thermometer decoder. If b
1
and b
0
both are equal to zero, all of the (+) inputs of interpolator DAC
6
are connected to Vlow, and the output Vout will then be equal to Vlow. If the digital input to the switching matrix
7
is 01, then the (+) input of one of the gm stages
8
-
1
,
2
,
3
,
4
is connected to Vhigh. Since one of 4 of the (+) inputs is connected to Vhigh, that gm stage adds an offset as indicated in the following equation:
V
out=
V
low+(
V
high−
V
low)/4(
b
1
b
0
=01)
When the LSB digital input b
1
b
0
is 10, two of the four (+) inputs of the gm inputs are connected to Vhigh. This causes interpolation DAC
6
to add yet another offset voltage to the output as indicated in the following equation:
V
out=
V
low+2*(
V
high−
V
low)/4(
b
1
b
0
=10)
When the LSB digital input b
1
b
0
is 11, three of the four (+) inputs of the gm stage are connected to Vhigh. This causes interpolation DAC
6
to add yet another offset voltage to the output as indicated in the following equation:
V
out=
V
low+3*(
V
high−
V
low)/4(
b
1
b
0
=11)
In general, for an N-bit interpolator, when k of the positive inputs (or thermometer-decoded LSBs) are connected to Vhigh, Vout will be given by the following equation:
V
out =
V
low+
k*
(
V
high−
V
low)/2
N
.
The foregoing equation indicates that linear interpolation is achieved between Vhigh and Vlow.
Thus, there is an unmet need for a circuit and method for reducing the INL of an interpolating string DAC, especially for an interpolating string DAC having a resolution of 16 bits or greater.
There also is an unmet need for a circuit and method for reducing the INL of an interpolating string DAC having a resolution of 16 bits or greater without use of precision resistors or laser trimming of resistors.
There also is an unmet need for an inexpensive interpolating string DAC, especially one having a resolution of 16 bits or greater, having very low integral nonlinearity.
There also is an unmet need for an inexpensive interpolating string DAC, especially one that has a resolution of 16 bits or greater and is compatible with present CMOS technologies.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide an inexpensive interpolating string DAC having very low integral nonlinearity, especially one having a resolution of 16 bits or greater.
It is another object of the present invention to provide a circuit and method for reducing the INL of an interpolating string DAC, especially for an interpolating string DAC having a resolution of 16 bits or greater.
It is another object of the present invention to provide a circuit and method for reducing the INL of an interpolating string DAC having a resolution of 16 bits or greater without use of precision resistors or laser trimming of resistors.
It is another object of the invention to provide an inexpensive interpolating string DAC that is suitable for manufacturing using a low-cost CMOS process.
Briefly described, and in accordance with one embodiment, the present invention provides an M+N bit DAC includes an N-bit interpolation circuit for interpolating between a first voltage (Vhigh) on a first conductor (
17
A) and a second voltage (Vlow) on a second conductor (
17
B), an output amplifier (
10
), a calibration interpolation circuit (
14
), a memory circuit (
36
) for storing error information corresponding to various values of the first voltage and second voltage, outputs of the N-bit interpolation circuit and the calibration interpolation circuit being coupled to inputs of the output amplifier, and switching circuitry responsive to a N-bit portion of a M+N input word coupling the memory to inputs of the of the calibration interpolation circuit so as to correct integral nonlinearity errors associated with the various values of the first and second voltages.
In the described embodiment, the invention provides an interpolation circuit for interpolating between a first voltage (Vhigh) on a first c

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