Radiant energy – Photocells; circuits and apparatus – Photocell controlled circuit
Reexamination Certificate
2001-05-16
2004-09-07
Luu, Thanh X. (Department: 2878)
Radiant energy
Photocells; circuits and apparatus
Photocell controlled circuit
C348S294000
Reexamination Certificate
active
06787754
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to solid-state image pickup devices and methods for fabricating the device. More particularly, the present invention relates to a solid-state image pickup device with a charge transfer electrode formed by processing an electrically conductive single-layer electrode material film, the device being provided with improved flatness without forming a thick oxide film on a peripheral device isolating region, and to a method for fabricating the solid-state image pickup device.
2. Description of the Related Art
FIG. 1
is a cross-sectional view illustrating a prior-art solid-state image pickup device with a single-layer electrode structure, showing the solid-state image pickup region of the prior-art solid-state image pickup, and the peripheral circuit region constituted by a transistor portion and a P well contact (P contact) portion.
There are formed P
+
regions
602
within the surface region of a P-type semiconductor substrate
601
. The device comprises the isolated portions of a solid-state image pickup region and a peripheral circuit region that is constituted by a transistor portion and a P well contact portion. On top of the P
+
regions
602
, there are formed field oxide films
614
, while gate insulating films
606
are formed on the surface of the P-type semiconductor substrate
601
in each device area. In this case, the device isolating region other than the solid-state image pickup region comprises the P
+
regions
602
and the field oxide films
614
. In the solid-state image pickup region, there is formed a P
+
isolating region
603
adjacent to the P
+
region
602
, adjacent to which further formed is a charge transfer portion
605
. On top of the gate insulating film
606
, there is formed a charge transfer electrode
627
. In addition, on the entire surface of the substrate
601
, there is formed an interlayer insulating film
610
through which formed are contact holes
612
that reach the charge transfer electrode
627
. A metal wiring
611
is formed through the contact holes
612
.
The transistor portion of the peripheral circuit region has two devices and two gate insulating films
606
. On top of one of the gate insulating films
606
, there is formed a gate electrode
637
. Below the other gate insulating film
606
, formed are T regions
608
acting as the source and drain region of the transistor portion. On the other gate insulating film
606
, the gate electrode
637
is formed so as to match between the N+regions
608
. The contact holes
612
are formed through the interlayer insulating film
610
formed on the entire surface of the substrate
601
to reach the N
+
regions
608
and the gate electrodes
637
. The metal wiring
611
is formed through the contact hole
612
.
In the P well contact portion of the peripheral circuit region, there is formed a P well contact portion
604
below the gate insulating film
606
. The contact holes
612
are formed through the interlayer insulating film
610
formed on the entire surface of the substrate
601
to reach the P well contact portion
604
. The metal wiring
611
is formed through the contact hole
612
.
FIGS. 2A
to
2
H are cross-sectional views illustrating a method for fabricating the prior-art solid-state image pickup device with the single-layer electrode structure, showing the steps of the method in orderly sequence. Now, the method for fabricating the prior-art solid-state image pickup device having the single-layer electrode structure shown in
FIG. 1
is explained below with reference to
FIGS. 2A
to
2
H.
First, as shown in
FIG. 2A
, the P
+
regions
602
are formed within the surface region of the P-type semiconductor substrate
601
. A nitride film
616
is used as a mask and a pad oxide film
615
is scrolled to implant ions into the P
+
regions
602
.
Then, as shown in
FIG. 2B
, the surface of the substrate is subjected to a heat treatment, for example, in an atmosphere of steam at 980° C. to form the field oxide film
614
. During this treatment, the region over which the nitride film
616
has been formed is not oxidized. For example, the field oxide film
614
is provided with a thickness of 800 to 1000 nm.
Then, as shown in
FIG. 2C
, an ion implantation such as of boron is performed to form the P
+
isolating region
603
for isolating a device from another in the solid-state image pickup region, and the P well contact portion
604
formed in the peripheral circuit region.
Then, as shown in
FIG. 2D
, for example, a phosphorous ion implantation is performed to form the N-type region acting as the charge transfer portion
605
.
Subsequently, as shown in
FIG. 2E
, the insulating film on the surface of the P-type semiconductor substrate other than the field oxide film
614
is removed to form again the gate insulating films
606
. Then, a polysilicon layer acting as a charge transfer electrode material film is formed through the gate insulating film
606
and patterned to form the charge transfer electrode
627
and the gate electrodes
637
of the transistor in the peripheral circuit region. Then, as shown in
FIG. 2F
, for example, an arsenic ion implantation is performed to form the N
+
region
608
serving as the SD (Source-Drain) of the transistor portion. Subsequently, as shown in
FIG. 2G
, the interlayer insulating film
610
is formed on the entire surface of the device. Then, as shown in
FIG. 2H
, the contact holes
612
are formed. Finally, as shown in
FIG. 1
, the metal wirings
611
are formed.
In the prior-art solid-state image pickup device with a single-layer electrode structure, the device isolating region other than the solid-state image pickup region was provided with thick field oxide films
614
, thereby being made high above the substrate surface of the device as well as causing significant irregularities on the device surface.
In the solid-state image pickup device, an on-chip micro-lens is provided for each pixel in order to increase the power of focusing light onto the pixel. For this purpose, the device surface has to be made flat. Thus, significant heights of the device and irregularities on the surface would lead to a thicker flattening film. This would produce a defocusing effect of the light condensed by the micro-lens on the photoelectric conversion region formed in the substrate, thereby resulting in a drop in sensitivity. In particular, an increase in diagonally incident light would lead to a more significant drop in sensitivity.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a solid-state image pickup device and a method for fabricating the device which is provided with improved flatness without forming a thick oxide film on the device isolating region around the device, which reduces the thickness of the flattening film required for flattening the device upon formation of the micro-lens, and which provides an improved sensitivity property especially upon incidence of light in diagonal directions onto the solid-state image pickup device.
A solid-state image pickup device according to the present invention comprises first and second insulating films formed on a surface of a semiconductor substrate; a solid-state image pickup region having, as a charge transfer electrode, an electrically conductive single-layer material film formed on the first insulating film; and a peripheral circuit region formed on the semiconductor substrate other than in the solid-state image pickup region. The solid-state image pickup device is characterized in that a device in the peripheral circuit region is isolated from another by means of an isolating electrode on the second insulating film, and the isolating electrode is formed of the single-layer conductive material film.
A gate electrode constituting a transistor in the peripheral circuit region is formed on the first insulating film in the peripheral circuit region, and the gate electrode is formed in the same step as that of the
Hatano Keisuke
Nakashiba Yasutaka
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