Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2003-01-29
2004-07-06
Elms, Richard (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
C365S171000
Reexamination Certificate
active
06760244
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory device, and more specifically, it relates to a memory device such as a magnetic memory device including storage elements exhibiting a ferromagnetic tunnel effect or the like.
2. Description of the Background Art
An MRAM (magnetic random access memory), i.e., a nonvolatile memory recording data through magnetism, is known in general. This MRAM is disclosed in Nikkei Electronics, 1999. 11. 15 (No. 757), pp. 49-56 or the like in detail.
FIGS. 7 and 8
are schematic diagrams for illustrating the structure of a storage element
110
forming the MRAM disclosed in the aforementioned literature. Referring to
FIG. 7
, the storage element
110
of the conventional MRAM comprises a ferromagnetic layer
101
, another ferromagnetic layer
103
and a non-magnetic layer
102
arranged between the ferromagnetic layers
101
and
103
.
The ferromagnetic layer
101
is harder to invert than the ferromagnetic layer
103
. The term “ferromagnetism” denotes such magnetism that magnetic atoms or free atoms of a metal parallelly align magnetic moments due to positive exchange interaction for forming spontaneous magnetization, and a substance exhibiting such ferromagnetism is referred to as a ferromagnetic substance. The ferromagnetic layers
101
and
103
consist of such a ferromagnetic substance. In general, the non-magnetic layer
102
is formed by a GMR (giant magnetoresistance) film employing a metal. A TMR (tunneling magnetoresistance) film employing an insulator has recently been developed as the non-magnetic layer
102
. The TMR film advantageously has larger resistance than the GMR film. More specifically, the MR ratio (resistance change) of the GMR film is on the 10% mark, while that of the TMR film is at least 20%. The storage element
110
consisting of the TMR film is hereinafter referred to as a TMR element
110
.
The storage principle of the conventional MRAM employing the TMR element
110
is now described with reference to
FIGS. 7 and 8
. First, the state where the directions of magnetization of the two ferromagnetic layers
101
and
103
are identical to each other (parallel) is associated with data “0”, as shown in FIG.
7
. The state where the directions of magnetization of the two ferromagnetic layers
101
and
103
are opposite to each other (antiparallel) is associated with data “1”, as shown in FIG.
8
. The TMR element
110
exhibits small resistance (R
0
) when the directions of magnetization are parallel, while exhibiting large resistance (R
1
) when the directions of magnetization are antiparallel. The MRAM determines whether the data is “0” or “1” through the property of the TMR element
110
exhibiting different resistance values in response to the directions of magnetization.
FIG. 9
is a block diagram showing the overall structure of a conventional MRAM
150
having memory cells each formed by a single TMR element and a single transistor. The structure of the conventional MRAM
150
is now described with reference to FIG.
9
.
A memory cell array
151
is formed by arranging a plurality of memory cells
120
in the form of a matrix (
FIG. 9
shows only four memory cells
120
, in order to simplify the illustration). Each memory cell
120
is formed by a single TMR element
110
and a single NMOS transistor
111
.
In the memory cells
120
arranged in a row direction, the gates of the NMOS transistors
111
are connected to common read word lines RWL
1
to RWL
n
. In the memory cells
120
arranged in the row direction, further, rewrite word lines WWL
1
to WWL
n
are arranged on first ferromagnetic layers of the TMR elements
110
.
In the memory cells
120
arranged in a column direction, first ferromagnetic layers of the TMR elements
110
are connected to common bit lines BL
1
to BL
n
.
The read word lines RWL
1
to RWL
n
are connected to a row decoder
152
, and the bit lines BL
1
to BL
n
are connected to a column decoder
153
.
Externally specified row and column addresses are input in an address pin
154
. The address pin
154
transfers the row and column addresses to an address latch
155
. In the row and column addresses latched in the address latch
155
, the row address is transferred to the row decoder
152
through an address buffer
156
, and the column address is transferred to the column decoder
153
through the address buffer
156
.
The row decoder
152
selects a read word line RWL corresponding to the row address latched in the address latch
155
from among the read word lines RWL
1
to RWL
n
, while selecting a rewrite word line WWL corresponding to the row address latched in the address latch
155
from among the rewrite word lines WWL
1
to WWL
n
. The row decoder
152
further controls the potentials of the read word lines RWL
1
to RWL
n
and the rewrite word lines WWL
1
to WWL
n
on the basis of a signal from a voltage control circuit
157
.
The column decoder
153
selects a bit line BL corresponding to the column address latched in the address latch
155
from among the bit lines BL
1
to BL
n
, while controlling the potentials of the bit lines BL
1
to BL
n
on the basis of a signal from another voltage control circuit
158
.
Externally specified data is input in a data pin
159
. The data pin
159
transfers the data to the column decoder
153
through an input buffer
160
. The column decoder
153
controls the potentials of the bit lines BL
1
to BL
n
in correspondence to the data.
Data read from an arbitrary memory cell
120
is transferred from any of the bit lines BL
1
to BL
n
to a sense amplifier group
161
through the column decoder
153
. The sense amplifier group
161
is formed by current sense amplifiers. The data determined by the sense amplifier group
161
is output from an output buffer
162
through the data pin
159
.
A control core circuit
163
controls the aforementioned operations of the circuits
152
to
162
.
A write (rewrite) operation and a read operation of the conventional MRAM
150
having the aforementioned structure are now described.
(Write Operation)
In the write operation, the MRAM
150
feeds orthogonal currents to the selected rewrite word line WWL and the selected bit line BL. Thus, data can be rewritten only in the TMR element
110
located on the intersection between the rewrite word line WWL and the bit line BL. More specifically, the currents flowing through the rewrite word line WWL and the bit line BL form magnetic fields, so that the sum (composite field) of the two magnetic fields acts on the TMR element
110
. The directions of magnetization of the TMR element
110
change from “1” to “0”, for example, due to the composite field.
The remaining TMR elements
110
located on intersections excluding the aforementioned one include those fed with absolutely no currents and those fed with only unidirectional currents. In each TMR element
110
fed with no current, no magnetic fields are formed and hence the directions of magnetization remain unchanged. In each TMR element
110
fed with only a unidirectional current, formed magnetic fields are insufficient in strength for inverting the directions of magnetization. Therefore, the directions of magnetization remain unchanged also in the TMR element
110
fed with only a unidirectional current.
As hereinabove described, the MRAM
150
can write the directions of magnetization of the TMR element
110
located on the intersection between the selected bit line BL and the selected rewrite word line WWL as shown in
FIG. 7
or
8
by feeding the currents to the bit line BL and the rewrite word line WWL corresponding to the selected address. Thus, the MRAM
150
can write data “0” or “1”.
(Read Operation)
In order to read the data written in the aforementioned manner, the MRAM
150
applies a voltage to the read word line RWL for rendering the NMOS transistor
111
conductive. In this state, the MRAM
150
determines whether the value of the current flowing through the bit line BL is larger or smaller than a reference current value, thereby determini
Elms Richard
Nguyen Tuan T.
Sanyo Electric Co,. Ltd.
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