Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2002-04-19
2004-07-20
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S425000, C438S439000, C438S443000, C438S452000
Reexamination Certificate
active
06764920
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of microelectronic integrated circuits. Specifically, the present invention relates to a process for reducing shallow trench isolation edge thinning on tunnel oxides for high performance flash memories.
2. Related Art
A flash or block erase memory (flash memory), such as, Electrically Erasable Programmable Read-Only Memory (Flash EEPROM), includes an array of cells which can be independently programmed and read. The size of each cell and thereby the memory as a whole are made smaller by eliminating the independent nature of each of the cells. As such, all of the cells are erased together as a block.
A memory of this type includes individual Metal-Oxide Semiconductor (MOS) memory cells, each of which includes a source, drain, floating gate and control gate to which various voltages are applied to program the cell with a binary 1 or 0, or erase all of the cells as a block.
As flash memory technology progresses, the density of the memory cells, as well as, the speed of the flash memory increases. Device isolation is necessary in order to achieve higher cell densities. Without proper device isolation, local cells as well as peripheral devices will adversely interfere and interact with each other. Device isolation helps reduce parasitic conduction paths, series resistances, current leakage, and helps maintain threshold voltage control.
Shallow trench isolation (STI) is one technique for device isolation. The STI technique improves the scaling of devices in order to increase cell density throughout the circuit. Currently, the formation of STI precedes the formation of tunnel oxide during device fabrication in the integrated circuit. Further, various clean and etch steps are performed on sacrificial oxide layers prior to tunnel oxide formation in order to achieve a good silicon surface for tunnel oxidation.
However, STI techniques in the prior art undesirably result in tunnel oxide edge thinning at the corners of the memory cell near the boundary with the STI field oxide. More specifically, the cleaning and etching of the sacrificial oxide layers usually consume the STI field oxide and thus lead to STI recess at the corners of the memory cell near the boundary with the STI field oxide. The STI recess in turn leads to the tunnel oxide edge thinning.
Prior Art
FIG. 1
is a cross-sectional view of an integrated circuit
100
containing a flash memory device. The portion illustrated in the flash memory device is the active region
120
containing either the source or drain. A tunnel oxide layer
110
is placed on top of the active region
120
. Also an STI trench region
130
is shown separating the active region
120
of the flash memory device from other devices, including peripheral devices.
Prior Art
FIG. 1
illustrates the thinning of the tunnel oxide region
110
at the corner of the active region
120
of the flash memory device. Distance B in the tunnel oxide region
110
at the corner of the active region
120
is shown to be thinner than distance A, which lies beyond the corner.
Tunnel oxide edge thinning at the corner of the active region
120
of the flash memory device results in poorer memory cell performance, such as, current leakage and fast bit memory erase. More specifically, the fast bit memory erase results in a non-uniform erase of the memory cells throughout the circuit Those cells with fast bit erase tendencies have a lower than desired threshold voltages. Furthermore, the tunnel oxide edge thinning can lead to other performance issues, such as, enhanced gate leakage current, over-erase, decreased gate oxide charge to breakdown, reduced long term oxide integrity, etc.
Thus, a need exists for a fabrication technique that provides better distribution of the tunnel oxide layer on a flash memory device. A further need exists for a fabrication technique that provides less tunnel oxide edge thinning at the corners of a flash memory device near the STI region.
SUMMARY OF THE INVENTION
The present invention provides a method of semiconductor structure fabrication wherein the method provides better distribution of a tunnel oxide layer on a flash memory device. Also, the present invention provides for a method of semiconductor fabrication that provides less tunnel oxide edge thinning at the shallow trench isolation (STI) corners of a flash memory device where the STI region and a top surface of the silicon substrate in the active source/drain region of a flash memory device converge.
Specifically, one embodiment of the present invention discloses a method for reducing shallow trench isolation (STI) corner recess of silicon in order to reduce STI edge thinning on tunnel oxides for flash memories. An STI process is implemented to isolate semiconductor devices in an integrated circuit in a semiconductor structure. In the STI process, a nitride layer is deposited over a silicon substrate. An STI region is formed in the silicon substrate defining STI corners where a top surface of the silicon substrate and the STI region converge. The STI region is filled with an STI field oxide. The STI field oxide is planarized until reaching the nitride layer. A local oxidation of silicon (LOCOS) is performed to oxidize the top surface of the silicon substrate that is under the nitride layer and adjacent to the STI corners.
The local oxidation forms an oxidized layer of silicon at the STI corners in a LOCOS bird's beak formation to boost the thickness of a later deposited or thermally grown tunnel oxide layer on a semiconductor flash memory device. The LOCOS process forms a small bird's beak formation. In one embodiment, to aid in the oxidation of the silicon in the bird's beak formation, the nitride layer is partially stripped down to a thickness of approximately 700 Angstroms. The partial stripping of the nitride layer also allows for control of the amount of field oxide within the STI region.
These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.
REFERENCES:
patent: 4683640 (1987-08-01), Faraone
patent: 4986879 (1991-01-01), Lee
patent: 5679599 (1997-10-01), Mehta
patent: 5811346 (1998-09-01), Sur et al.
patent: 6087243 (2000-07-01), Wang
patent: 6503815 (2003-01-01), Hsu
Kim Unsoon
Wang John Jianshi
Yang Nian
Rocchegiani Renzo
Smith Matthew
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