Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2002-10-30
2004-04-13
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S784000
Reexamination Certificate
active
06720658
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a multi-layer wiring structure made by a damascening process or a dual damascening process, and a method of manufacturing such a device.
An ultra-large scale integrated circuit (ULSI) employs a multilayer wiring structure in which wiring layers of three levels or more are formed.
FIGS. 1 and 2
show a semiconductor device prepared by a conventional wiring process.
FIG. 2
is a cross sectional view taken along the line II—II indicated in FIG.
1
.
As can be seen in the figure, a field oxide layer
12
is formed on a semiconductor substrate
11
. In an element region surrounded by the field oxide layer
12
, a MOS transistor having a source-drain region
13
and a gate electrode
14
, is formed.
On the semiconductor substrate
11
, an insulating layer
15
is formed so as to completely cover the MOS transistor. A contact hole
16
is made in the insulating layer
15
from its surface to be through to the source-drain region
13
. On the insulating layer
15
, a first-level wiring layer having a plurality of wiring layers
17
is formed. Each of the plurality of wiring layers
17
is connected to the source-drain region
13
of the MOS transistor via the contact hole
16
.
On the insulating layer
15
, an insulating layer (interlayer dielectric)
18
is formed so as to completely cover the plurality of wiring layers
17
. A contact hole
19
is made in the insulating layer
18
from its surface to be through to the plurality of wirings
17
. On the insulating layer (interlayer dielectric)
18
, a second-level wiring layer having a plurality of wiring layers
20
is formed. Each of the plurality of wiring layers
20
is connected to the wiring layers
17
of the first-level wiring layers via the contact hole
19
.
On the insulating layer (interlayer dielectric)
18
, a bonding pad
21
is formed. Further, on the insulating layer (interlayer dielectric)
18
, an insulating layer (passivation dielectric)
22
is formed so as to completely cover the plurality of wiring layers
20
and the bonding pad
21
. An opening
23
is made in the insulating film (passivation dielectric)
22
so as to expose the bonding pad
21
.
In a semiconductor device manufactured by the conventional wiring process., a plurality of wirings
17
of the first-level wiring layer, a plurality of wirings
20
of the second-level wiring layer and the bonding pad
21
are formed by a photo engraving process (PEP), in which, a resist pattern is formed, and using the resist pattern as a mask, metal layers are etched by an anisotropic etching (such as RIE).
However, in an ULSI, the distance between wirings of the same level is becoming very narrow.
Therefore, the following drawbacks begin to arise.
First, it is very difficult to accurately pattern the wirings
17
and
20
of the wiring layers. This is because the resolution of the exposing device for forming resist patterns, cannot follow up wiring patterns which are becoming finer as the technology develops.
Second, it is very difficult to fill grooves resulting between wirings of the same level, with insulating layer, and therefore cavities are inevitably created between the wirings. This is because of a poor step coverage of the insulating layer. Such cavities adversely affect the multilayer wiring technique.
FIGS. 3 and 4
show a semiconductor device manufactured by a dual damascening process.
FIG. 4
is a cross sectional view taken along the line IV—IV indicated in FIG.
3
.
As can be seen in the figure, a field oxide layer
12
is formed on a semiconductor substrate
11
. In an element region surrounded by the field oxide layer
12
, a MOS transistor having a source-drain region
13
and a gate electrode
14
, is formed.
On the semiconductor substrate
11
, insulating layers
15
and
24
are formed so as to completely cover the MOS transistor. A contact hole
16
is made in the insulating layers
15
and
24
from its surface to be through to the source-drain region
13
.
The insulating layer
25
is formed on the insulating layer
24
. In the insulating layer
25
, a plurality of grooves
16
b
used for forming a first-level wiring layer, is formed. Bottom sections of the plurality of grooves
16
b
are made through to the contact hole
16
a.
A barrier metal
17
a
is formed on an inner surface of each of the contact hole
16
a
and the grooves
16
. Further, on each of the barrier metals
17
a
, a metal (or metal alloy) portion
17
b
is formed so as to completely fill each of the contact hole
16
a
and the grooves
16
b
. The plurality of wirings which make the first level wiring layer, consist of the barrier metals
17
a
and the metal portions
17
b.
The surface of the insulating layer
25
meets with that of the first-level wiring layer, and the surface is made flat. Each of the plurality of wirings which give rise to the first-level wiring layer, is connected to the source-drain region
13
of the MOS transistor.
On the insulating layer
25
and the first level wiring layer, the insulating layer (interlayer dielectric)
18
and the insulating layer
26
are formed. A contact hole
19
a
is formed in the insulating layers
18
and
26
from its surface to be through to the first-level wiring layer.
An insulating layer
27
is formed on the insulating film
26
. A plurality of grooves
19
b
used for forming the second-level wiring layer, are formed in the insulating layer
27
. Bottom sections of the plurality of grooves
19
b
are made through to the contact hole
19
a.
A barrier metal
20
a
is formed on an inner surface of each of the contact hole
19
a
and the grooves
19
b
. Further, on each of the barrier metals
20
a
, a metal (or metal alloy) portion
20
b
is formed so as to completely fill each of the contact hole
19
a
and the grooves
19
b
. The plurality of wirings which make the second level wiring layer, consist of the barrier metals
20
a
and the metal portions
20
b.
The surface of the insulating layer
27
meets with that of the second-level wiring layer, and the surface is made flat. Each of the plurality of wirings which give rise to the second-level wiring layer, is connected to the first-level wiring layer.
In the case where the second-level wiring layer is located as the uppermost layer, a part of the second-level wiring layer constitutes a bonding pad
21
. The bonding pad
21
is made of a metal (or metal alloy), as in the case of the second-level wiring layer.
An insulating layer (passivation dielectric)
22
is formed on the insulation layer
27
, the second-level wiring layer and the bonding pad
21
. An opening
23
is made in the insulating layer
22
so as to expose the bonding pad
21
.
Regarding the semiconductor device manufactured by the dual damascening process as described above, it is able to solve the drawbacks of the conventional wiring process, that is, the wiring pattern becoming out of focus when exposing, and the cavities resulting between wirings.
However, in the dual damascening process or damascening process, the chemical mechanical polishing (CMP) technique is employed. In the case where a bonding pad
21
is formed by the CMP technique, the central portion of the bonding pad
21
is excessively etched, resulting in dishing, that is, the bonding pad
21
is made into a dish-like shape.
FIG. 5
illustrates how dishing occurs.
More specifically, the CMP not only mechanically etch the metal layer
21
′, but also chemically etch it. Therefore, in the case where the metal layer
21
(bonding pad) remains in a groove
19
b
which has a width sufficiently large as compared to its depth (note that the size of a bonding pad is usually about 100 &mgr;m×100 &mgr;m), the central portion of the metal layer
21
in the groove
19
b
is excessively etched mainly by chemical etching.
Such dishing easily causes a bonding error, that is, a wire cannot be bonded to the bonding pad
21
accurately during a wiring bonding operation, which results in the deterioration of the production yield.
FIGS. 6 and 7
show a s
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