Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-12-14
2004-04-13
Le, Thong Q. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185240
Reexamination Certificate
active
06721205
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device having a memory cell provided with a storage portion comprised of films having a charge storing capability at both of the two impurity regions forming a source or drain and capable of recording 2 bits of data per cell and methods for operating and producing the same.
2. Descriptions of the Related Art
As a nonvolatile semiconductor memory device, there is well known, for example, a so-called metal-oxide-nitride-oxide-semiconductor (MONOS) type memory or a metal-nitride-oxide-semiconductor (MNOS) type wherein, as a charge storing means for storing data, an insulating film formed by stacking a plurality of films is provided. In the MONOS type memory device, an oxide-nitride-oxide(ONO) film and a gate electrode are stacked on a semiconductor forming a transistor channel, for example, a semiconductor substrate, a well, or a silicon on insulator (SOI) layer (hereinafter referred to merely as a “substrate”) and source and drain regions having a conductivity type opposite to the substrate are formed in surface regions of the substrate at the two sides of the stacked pattern.
By injecting a charge into an insulating film having a charge storing capability from the substrate side, writing of data is performed. Erasure is achieved by extracting the stored charge to the substrate side or by injecting an opposite polarity charge into the insulating film to cancel the stored charge.
For injection of the charge into the isolation film, there is known a method of using a charge tunneling phenomenon caused inside an insulator and also, for example, so-called channel-hot-electron (CHE) injection and other methods of exciting a charge in energy up to a degree capable of overcoming the insulating barrier of the bottommost oxide film of an ONO film and so on.
Recently, technology taking note of the fact that conventional CHE injection enables injection of a charge into part of a discrete trap area including dispersed charge traps, and enabling storage of 2 bits per memory cell by independently writing binary data to a source side and a drain side of a charge storing means, that is, the stacked insulating film having the charge storing capability, has been reported.
For example, Extended Abstract of the 1999 International Conference on Solid State Device and Materials, Tokyo, 1999, pp. 522-523, considers that it is possible to reliably read 2 bits of data of small amounts of stored charges by the so-called “reverse read” method by changing the direction of the voltage applied between the source and the drain to write 2 bits of data by CHE injection and, when reading, applying a specified voltage between the source and the drain in a direction reverse to that of the write operation to independently read the 2 bits of data. Further, erasure is performed by forming an inversion layer in a surface region of the source or drain impurity region, causing a high energy charge (hot holes) by avalanche breakdown in the inversion layer, and injecting the hot holes into the charge storing means.
By using this technique, it becomes possible to increase the write speed and greatly reduce the cost per bit.
However, in this memory cell able to store 2 bits of data using conventional CHE injection, the charge storing film (ONO film) is formed on the entire surface of the channel forming region, so the region in which the charge is injected is not limited. Therefore, when the amount of stored charge fluctuates due to the process of the device or nonuniformity of the-bias conditions at the time of operation, this easily can have a delicate effect on the storage characteristics, for example, the change in the threshold voltage. Particularly, when more than the required charge is injected, the change in characteristic at the over-write side becomes a problem since the charge storage region is not limited. Further, since the charge storage region is not limited, there is the disadvantage that the erasure time also becomes long.
Further, a charge trapped in a carrier trap of the charge storing film itself moves much less easily than a charge in a conductive layer, but if the device is held at a high temperature for a long period, so-called “dilution” of storage will occur where there is a certain drift due to heat and the charge retention region expands. In this case as well, in a conventional device structure where the charge storing film is formed uniformly with respect to the entire channel forming region, the relative magnitude of the threshold voltages changes delicately.
There is known that the efficiency of charge injection in conventional CHE injection is a poor one of about 1×10
−6
. Thus, in a write operation, a large current is required to be passed between the source drain regions in the memory cell. Therefore, there was the problem of the power consumption becoming larger.
On the other hand, in the above conventional memory cell structure, when using a so-called virtual ground (VG) cell array, one type of array with the smallest cell area, while random access makes it possible to enable selection of any one of a plurality of memory cells connected to a single word line, it suffers from the disadvantage that serial access for simultaneously accessing a plurality of memory cells is not possible.
This is due to the fact that in a VG cell array, the source and the drain regions are shared between two adjoining memory cells in the word line direction. This shared relation is repeated in the word line direction. Namely, in a VG cell array, viewed in the word line direction, source and drain regions and channel forming regions having different conductivity types are alternately repeated. Therefore, when determining the voltages in the two source and drain regions in a certain memory cell, to prevent unintentional operation of other memory cells of the same row, the potentials of the other source and drain regions are also inevitably determined. Therefore, leaving aside memory cells for which the intended operation is possible coincidentally under the relative potentials, access to other memory cells basically becomes impossible. Further, conditional serial access where the accessible cells are constantly changing depending on the logic of the stored data is not practical.
For the above reason, when constructing a VG cell array by memory cells of the above conventional structure, it is not possible to freely and independently operate a plurality of memory cells connected to the same word line. As the result, with conventional memory cells, when constructing a VG cell array so as to reduce the cell area, it suffers from the disadvantage of a large number of write operations when writing data to all memory cells connected to one word line and a longer total time required for writing. That is, the superiority in the reduction of the bit cost obtained by use of a VG cell array to reduce the cell area ends up becoming smaller when not using a VG cell array and raising the write efficiency by serial access.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a nonvolatile semiconductor memory device which limits the range of a charge retention region which can store 2 bits of data and is less influenced in characteristics even if an excessive charge is injected and methods for operating and producing the same.
A second object of the present invention is to provide a nonvolatile semiconductor memory device which is raised in efficiency of charge injection, improved in write speed, and reduced in the power consumed by a memory cell in a write operation and methods for operating and producing the same.
A third object of the present invention is to provide a nonvolatile semiconductor memory device which is provided with a means for controlling an ON/OFF state of a channel separate from a normal gate electrode of a memory transistor and which thereby enables serial access of a plurality of memory cells connected with one word line even when using a VG cell arr
Fujiwara Ichiro
Kobayashi Toshio
Moriya Hiroyuki
Kananen Ronald P.
Le Thong Q.
Rader & Fishman & Grauer, PLLC
Sony Corporation
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