Snap-back preventing method for high voltage MOSFET

Details Snap-back preventing method for high voltage MOSFET Snap-back preventing method for high voltage MOSFET

1992-03-30

1993-02-09

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 57, 437 74, 437 29, 148DIG126, 257375, 257901, 257928, H01L 21265

Patent

active

051852756

ABSTRACT:
A process for improving the high voltage performances of a MOSFET transistor, and suppressing parasitic current induced snap-back behavior by placing a heavily doped P+ region around the grounded source. A first P+ region is placed adjacently to and in contact with the source and its metal lead, and a second P+ region may be placed under and in contact with the source and first P+ region, or form a layer under the entire transistor connected to the source by a P+ plug. Additional grounding of the source may be accomplished by a succession of alternating P+ region and N+ regions along the source edge.

REFERENCES:
patent: 4797724 (1989-01-01), Boler et al.

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