Pulse or digital communications – Receivers – Angle modulation
Reexamination Certificate
2000-03-27
2004-03-02
Chin, Stephen (Department: 2634)
Pulse or digital communications
Receivers
Angle modulation
C375S373000, C375S334000
Reexamination Certificate
active
06700941
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a digital demodulation apparatus, and more particularly, to a digital demodulation apparatus for demodulating a frequency-modulated bi-phase signal.
FIG. 1
is a schematic block diagram of a digital demodulation circuit
100
, and
FIG. 2
is a chart showing the waveforms of signals handled by the demodulation circuit
100
of FIG.
1
.
A bi-phase signal BS is inverted every predetermined r data period T and is either inverted or maintained during the predetermined period T to represent binary information. For example, with reference to
FIG. 2
, the binary information inverted at the middle of the data period T represents “1” and the binary information maintained in the same state during the data period T represents “0”. Frequencies are switched in accordance with the shifting of the bi-phase signal BS between a high level and a low level to frequency-modulate the bi-phase signal BS. For example, if the frequency of a carrier wave is 20 kHz, a modulated signal MS that is 2 kHz higher is generated when the bi-phase signal BS is high, and 2 kHz lower when the bi-phase signal BS is low. In other words, the modulated signal MS includes a high frequency component, which has a high level and is higher than the carrier wave frequency, and a low frequency component, which has a low level and is lower than the carrier wave frequency. The two frequency components of the modulated signal MS are mixed in a time-dividing manner.
The demodulation circuit
100
includes a pulse width counter
1
, a bandpass filter
2
, a code determiner
3
, and a phase-locked loop
4
. The pulse width counter
1
measures the cycle of the modulated signal MS by performing a count operation based on a clock signal having a frequency that is significantly higher than the carrier frequency of the modulated signal MS to generate digital cycle information PW
0
. For example, by performing a count operation and by resetting the count value each time the modulated signal MS exceeds a predetermined threshold value, the cycle information PW
0
, the value of which is updated every cycle of the modulated signal MS, is generated.
The bandpass filter
2
eliminates high frequency components included in the cycle information PW
0
due to noise and direct current components from the cycle information PW
0
provided by the pulse width counter
1
to generate a cycle signal PW
1
, which includes a frequency component that is substantially the same as the carrier wave frequency of the modulated signal MS. That is, when noise is included in the modulated signal MS thereby temporarily offsetting its cycle, high frequency components, which should not be included in the modulated signal MS, are eliminated from the cycle information PW
0
to prevent erroneous functioning. Further, direct current components are eliminated from the cycle information PW
0
to generate the cycle signal PW
1
, which indicates changes in the carrier frequency.
The code determiner
3
determines whether the code of the cycle signal PW
1
provided from the bandpass filter
2
is positive or negative and generates the bi-phase signal BS. The code of the cycle signal PW
1
represents the difference between the frequency of the modulated signal MS and the carrier frequency. Accordingly, the code indicates whether the modulated signal MS is high or low.
The phase-locked loop
4
uses the bi-phase signal BS as a reference signal to generate a bi-phase clock signal BC having a cycle that is one half the data period T of the bi-phase signal BS. The bi-phase clock signal BC is used by a signal processing circuit connected to the demodulation circuit
100
to retrieve and determine the bi-phase signal BS. That is, the signal processing circuit retrieves the bi-phase signal BS in accordance with the rising of the bi-phase clock signal BC and determines the data based on changes in the bi-phase signal BS.
The bi-phase signal BS does not rise and fall according to a constant cycle. Thus, the phase-locked loop
4
performs phase comparison between a certain rising edge or falling edge of the bi-phase signal BS and an oscillation clock. In this case, the oscillation clock may be locked at an erroneous frequency since it may be determined that there is no phase difference between the oscillation clock and the bi-phase signal regardless of the cycle of the bi-phase signal BS being an integer times greater than that of the oscillation clock. Accordingly, in addition to phase comparison, it is required that PLL control be performed so that the frequency of the oscillation clock matches the frequency of the bi-phase signal BS. However, the frequency comparison process is more complicated than phase comparison. This complicates the circuit configuration and increases the circuit area of the phase-locked loop
4
.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a digital demodulation apparatus that performs a stable oscillation operation and has a simple circuit configuration.
A first aspect of the present invention provides a digital demodulation apparatus. The digital demodulation apparatus includes a pulse width counter for measuring a cycle of a modulated signal to generate digital cycle information. A first digital filter is connected to the pulse width counter for equalizing the digital cycle information to generate averaged cycle information. A comparator is connected to the pulse width counter and the first digital filter for comparing the digital cycle information and the averaged cycle information to generate a bi-phase signal. A phase-locked loop generates a clock signal having a frequency according to the averaged cycle information and a phase being synchronized with the phase of the bi-phase signal.
A second aspect of the present invention provides a method for demodulating a bi-phase signal. First, a cycle of a modulated signal is measured to generate digital cycle information. The digital cycle information is equalized to generate averaged cycle information. Then, the digital cycle information and the averaged cycle information are compared to generate a bi-phase signal. A clock signal having a frequency according to the averaged cycle information and a phase being synchronized with the phase of the bi-phase signal is then generated.
REFERENCES:
patent: 5920214 (1999-07-01), Lee et al.
Chin Stephen
Fish & Richardson P.C.
Odom Curtis
Sanyo Electric Co,. Ltd.
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