Semiconductor memory device and method for selecting...

Details Semiconductor memory device and method for selecting... Semiconductor memory device and method for selecting...

2003-02-13

2004-09-07

Mai, Son L. (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S220000, C365S230060, C365S230080, C365S189080, C365S207000

Reexamination Certificate

active

06788610

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly, to a method for testing for interference between adjacent cells that reduces time and prevents noise.
An adjacent cell interference test is conducted on semiconductor devices, especially DRAMs. During the adjacent cell interference test, a certain word line remains selected for a predetermined time, and a sense amplifier amplifies the cell information read from a bit line. Then, interference is detected from the cell information stored in a memory cell connected to the adjacent word line.
Due to the increase in the memory capacity of semiconductor memory devices, the number of word lines has increased. This has lengthened the time required to conduct the adjacent cell interference test. To save testing costs, it is required that the testing time be reduced. Therefore, a multiple word line selection test is conducted to simultaneously activate a plurality of word lines. In this test, it is required that the number of simultaneously selected word lines be increased and abnormal functioning caused by noise be prevented.
FIG. 1
is a circuit diagram of a memory cell array and its peripheral circuits in a semiconductor memory device (DRAM)
50
. The memory cell array has four memory cell blocks BL
0
, BL
1
, BL
2
, BL
3
. Sense amp groups
1
and row decoders
2
are adjacent to the blocks BL
0
-BL
3
. Each sense amp group
1
includes a plurality of sense amps
8
.
The peripheral circuits include sense amp drive circuits
3
, block control circuits
4
, a timing signal generation circuit
5
, a block address buffer
6
, and an address buffer
7
. The sense amp drive circuits
3
are each associated with one of the sense amp groups
1
. The block control circuits
4
are each associated with one of the blocks
0
-
3
.
The sense amp drive circuits
3
and the block control circuits
4
receive a timing signal from the timing signal generation circuit
5
. The block control circuits
4
receive a block address signal Bad from an external device via the block address buffer
6
.
The block control circuits
4
generate a word line set signal WLst, which activates word lines, and a word line reset signal WLrs, which inactivates word lines. Further, the block control circuits
4
provide the associated row decoders
2
with the set signal WLst and the reset signal WLrs.
Based on the timing signal and the block address signal Bad, the block control circuits
4
generate a block selection signal Bs
1
and provide the associated sense amp drive circuits
3
with the block selection signal Bs
1
. Based on the block selection signal Bs
1
, the sense amp drive circuits
3
provide the associated sense amp groups
1
with sense amp drive signals PSA, NSA.
The row decoders
2
receive a word line address signal WLad from an external device via the address buffer
7
. The row decoders
2
select word lines based on the word line address signal WLad and the word line set signal WLst and terminates the selection of word lines based on the word line reset signal WLrs.
FIG. 2
is a diagram showing the memory cell array and its peripheral circuits in a single memory cell block. The memory cell block includes, for example, 128 word lines WL
0
-WL
127
. A plurality of sense amps
8
are connected to bit lines BL, which intersect each of the word lines WL
0
-WL
127
.
In response to the block selection signal Bs
1
received from the block control circuit
4
, the sense amp drive circuit
3
provides each sense amp
8
with the sense amp drive signals PSA, NSA.
The row decoders
2
select word lines in response to the word line address signal WLad and the word line set signal WLst, which are provided in response to the word lines WL
0
-WL
127
. Further, in response to the word line reset signal WLrs, the row decoders
2
terminates the selection of word lines.
The block control circuits
4
, the sense amp drive circuits
3
, and the row decoders
2
will now be discussed with reference to FIG.
3
.
Each block control circuit
4
includes a block selection circuit
9
, a word line set signal generation circuit
10
, and a word line reset signal generation circuit
11
. The block selection circuit
9
receives the block address signal Bad at a high level and a block set timing signal Bstt at a high level. The timing signal Bstt is received from the timing signal generation circuit
5
. The block selection circuit
9
has a latch circuit
12
a
and two inverter circuits
13
a
to generate the block selection signal Bs
1
at a high level in response to the block address signal Bad and the high timing signal Bstt.
When the block selection circuit
9
receives a high block reset timing signal Brst from the timing signal generation circuit
5
, the latch circuit
12
a
and the inverter circuits
13
a
generate the block selection signal Bs
1
at a low level.
The word line set signal generation circuit
10
includes a NAND circuit
14
a
and an inverter circuit
13
b
. The NAND circuit
14
a
has a first input terminal, which receives the block selection signal Bs
1
, and a second input terminal, which receives a word line set timing signal WLstt from the timing signal generation circuit
5
. The inverter circuit
13
b
receives the output signal of the NAND circuit
14
a
and generates the word line set signal WLst.
When the word line set signal generation circuit
10
receives the block selection signal Bs
1
at a high level and the word line set timing signal WLstt at a high level, the word line set signal generation circuit
10
generates the word line set signal WLst at a high level.
The word line reset signal generation circuit
11
includes a NAND circuit
14
b
and inverter circuits
13
c
,
13
d
. The NAND circuit
14
b
has a first input terminal, which receives the block selection signal Bs
1
, and a second input terminal, which receives a word line reset timing signal WLrst from the timing signal generation circuit
5
via the inverter circuit
13
c
. The two inverter circuits
13
d
receive the output signal of the NAND circuit and generate the word line reset signal WLrs.
When the word line reset signal generation circuit
11
receives the block selection signal Bs
1
at a high level and the word line reset timing signal WLrst at a low level, the word line reset signal generation circuit
11
generates the word line reset signal WLrs at a low level. The word line reset signal generation circuit
11
generates the word line reset signal WLrs at a high level when such signals are not received.
The sense amp drive circuit
3
includes a NAND circuit
14
c
, inverter circuits
13
e
,
13
f
, and transistors Tr
1
-Tr
4
. The NAND circuit
14
c
has a first input terminal, which receives the block selection signal Bs
1
, and a second input terminal, which receives a sense amp timing signal SAt from the timing signal generation circuit
5
.
The output signal of the NAND circuit
14
c
is provided to the gates of the p-channel MOS transistor Tr
1
and the n-channel MOS transistors Tr
2
, Tr
3
via the two inverter circuits
13
e
. The output signal of the inverter circuit
13
e
is provided to the gate of the n-channel MOS transistor Tr
4
via the inverter circuit
13
f.
The transistors Tr
1
-Tr
4
are connected in series between power supplies Vcc and Vss. A sense amp drive signal PSA is generated at a node of the transistors Tr
1
, Tr
2
. A sense amp drive signal NSA is generated at a node of the transistors Tr
3
, Tr
4
. A node of the transistors Tr
2
, Tr
3
is supplied with precharge voltage Vp.
When the NAND circuit
14
C receives the block selection signal Bs
1
at a high level and the sense amp timing signal SAt at a high level, the transistors Tr
1
, Tr
4
are activated and the transistors Tr
2
, Tr
3
are inactivated. This generates the sense amp drive signal PSA at a voltage that is substantially the same as that of the power supply Vcc and the sense amp drive signal NSA at a voltage that is substantially the same as that of the power supply voltage Vss.
When either the block select

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