Multiplex communications – Pathfinding or routing – Through a circuit switch
Reexamination Certificate
2001-06-01
2004-04-13
Nguyen, Chau (Department: 2663)
Multiplex communications
Pathfinding or routing
Through a circuit switch
C370S392000, C370S401000
Reexamination Certificate
active
06721312
ABSTRACT:
FIELD OF THE INVENTION
The present invention is in the field of hardware and software for data packet routers and pertains particularly to methods for improving data processing rates within the router fabric of such data packet routers.
BACKGROUND OF THE INVENTION
With the advent and continued development of the well-known Internet network, and of similar data-packet networks, much attention has been paid to computing machines for receiving, processing, and forwarding data packets. Such computing machines, known as routers in the art, typically have multiple interfaces for receiving and sending packets, and circuitry coupled at each interface, including typically a packet processor, for handling and processing packets. The circuitry at the interfaces is typically implemented on modules known as line cards in the art, and all of the line cards are typically interconnected. In systems known to the present inventor interconnection is through what is known as the internal fabric, which comprises interconnected fabric cards.
A fabric card known to the inventor supports a plurality of ingress/egress data ports and a crossbar switching facility for switching traffic in the card from port to port. The ports and switching facility are implemented in the form of ASIC chips that are typically clocked in a synchronous mode according to a master clock signal.
The switching facility of the above-described fabric card is a bit-sliced ASIC partitioned into several identical slices known as cross-point ASICS (CPAs). Each slice is adapted to handle switched transmission of a bit portion of each data packet received from a sending port that is transmitting data destined for another port. Also included in this facility is a chip (ASIC) adapted to schedule communication between the ports on the card. This ASIC is termed a cross-point scheduling ASIC (CSA). This scheduling is accomplished, basically, on a per-request basis wherein a port issues a request to transmit on the card to a destination (another port) through the switching facility. When it is determined by the scheduling chip that the switching facility can support the switching and transmission of data (from ingress to egress), a grant is issued to the requesting port. The scheduling chip also programs each bit-slice of the facility to receive from the requesting port and to transmit to the receiving port.
The present apparatus and method known to the inventor operates in a manner that slices of a single packet are required to be sent synchronously, which imposes a unnecessary upper operating frequency limitation due to clock offset among clocked components. What is clearly needed is an apparatus and a method for managing data flow through a bit-sliced switching facility on a router fabric card that allows the CPAs to be used in a pseudo-synchronous way, improving the efficiency of use of the transmission mechanism.
SUMMARY OF THE INVENTION
In a preferred embodiment of the present invention a fabric card for routing data packets is provided, comprising a plurality of ingress/egress ports, a switching component through which the ports connect, and a scheduling component for scheduling communication between the plurality of ports through the switching component. The card is characterized in that data coming into one of the plurality of ports is organized into specific data packet trains each having a start-of-train (SOT) identifier and an end-of-train (EOT) identifier, and wherein the switching facility recognizes the SOT and the EOT identifiers switches transmission to a next port and train accordingly.
In some embodiments of the card the switching facility comprises a plurality of individual cross-point application-specific integrated circuits (CPAs). Also in some embodiments individual ones of the CPAs further comprise a queue for listing assignments for transmission. Further there may be data queues (D-FIFOs) following individual ones of the CPAs for buffering data flow to an egress port.
Also in some embodiments of the card each port receiving data requests authorization to transmit from the scheduling component, and also sends an almost done flag (ADF) to the scheduling component prior to the EOT. In some cases the scheduling component uses the ADF to trigger scheduling the sending port for a new transmission.
In another aspect of the invention a method for high-speed transmission of packet data from ingress to egress ports connected across a fabric card through a switching component is provided, comprising the steps of (a) organizing incoming data into a packet train and inserting therein additional data comprising a start of train (SOT) and an end of train (EOT) identifier; (b) requesting permission from a scheduling component to transmit the assembled packet train from ingress to egress on the card through the switching component; (c) upon receiving authorization to transmit by an ingress port, transmitting the assembled packet train through the switching component; and (d) upon recognizing the EOT of a packet train, switching transmission to a different packet train.
In some embodiments of the method the switching facility comprises a plurality of individual cross-point application-specific integrated circuits (CPAs), and individual ones of the CPAs may further comprise a queue for listing assignments for transmission. There may also be data queues (D-FIFOs) following individual ones of the CPAs, the queues buffering data flow to an egress port. Further, each port receiving data may request authorization to transmit from the scheduling component, and also send an almost done flag (ADF) to the scheduling component prior to the EOT. The scheduling component may also use the ADF to trigger scheduling the sending port for a new transmission. In yet another aspect of the invention a packet switching element is provided, comprising a plurality of ingress/egress ports, and data switching components between ports. The data coming into a first one of the plurality of ports is organized into specific data-packet trains each having a start-of-train (SOT) identifier and an end-of-train (EOT) identifier, and wherein the switching element recognizes the SOT and the EOT identifiers and switches transmission to a next port and train accordingly. In some embodiments of the switching element the data switching components comprise a plurality of individual cross-point application-specific integrated circuits (CPAs). Also in some embodiments individual ones of the CPAs further comprise a queue for listing assignments for transmission. In other embodiments each CPAs is capable of switching to a next port assignment of its own accord. In still other embodiments there are data queues (D-FIFOs) following individual ones of the CPAs for buffering data flow to an egress port.
In some cases each port receiving data requests authorization to transmit from a scheduling component, and also sends an almost done flag (ADF) to the scheduling component prior to the EOT, and in some cases the scheduling component uses the ADF to trigger scheduling the sending port for a new transmission.
In still another aspect of the invention a data packet router is provided, comprising external ingress/egress ports for receiving and sending data packets to and from neighboring routers, and one or more packet switching elements, each having a plurality of local ingress/egress ports and data switching components between the local ports. Data coming into a first one of the plurality of ports is organized into specific data-packet trains each having a start-of-train (SOT) identifier and an end-of-train (EOT) identifier, and wherein the switching element recognizes the SOT and the EOT identifiers and switches transmission to a next port and train accordingly.
In some embodiments of the router the data switching components comprise a plurality of individual cross-point application-specific integrated circuits (CPAs). In other embodiments individual ones of the CPAs further comprise a queue for listing assignments for transmission. In still other embodiments each CPAs is capable of sw
Niu I-Sing Roger
Tuck, III Russell R.
Wang Ying
Boys Donald R.
Central Coast Patent Agency Inc.
Hyun Soon-Dong
Pluris, Inc.
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