Method of manufacturing a vertical field effect transistor

Details Method of manufacturing a vertical field effect transistor Method of manufacturing a vertical field effect transistor

1994-06-01

1996-04-16

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 46, 437149, 148DIG126, H01L 21266

Patent

active

055082173

ABSTRACT:
A vertical type field effect transistor includes N-type base regions formed on the surface of a P-type semiconductor substrate, a P-type source region formed in each of the N-type base regions, a gate insulating film formed between the P-type source regions, and a gate electrode formed of polysilicon on the gate insulating film. The transistor has the P-type source regions, the N-type base regions and a lower portion of the P-type semiconductor substrate as three terminals. A method for manufacturing the transistor comprises the steps of: forming the gate insulating film; growing a polysilicon layer; performing ion injection of an N-type impurity for the grown polysilicon layer; and performing heat treatment after the ion injection.

REFERENCES:
patent: 4914047 (1990-04-01), Seki
patent: 5306654 (1994-04-01), Kometani
Ghandhi, "VLSI Fabrication Principles, Silicon & Gallium Arsenide", 1983, pp. 327-328.
Nonaka, Abstract of Japanese Unexamined Patent Publication Tokukaihei 1-260856, Oct. 1989.
Kunio, Abstract of Japanese Unexamined Patent Publication Tokukaihei 2-291174, Nov. 1990.

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