Processor capable of executing packed shift operations

Details Processor capable of executing packed shift operations Processor capable of executing packed shift operations

2001-02-14

2004-05-18

Malzahn, David H. (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C712S223000

Reexamination Certificate

active

06738793

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
In particular, the present invention describes an apparatus for performing arithmetic and logical operations using a single control signal to manipulate multiple data elements. The present invention allows execution of shift operations on packed data types and also allows execution of alignment operations.
2. Description of Related Art
Today, most personal computer systems operate with one instruction to produce one result. Performance increases are achieved by increasing execution speed of instructions and the processor instruction complexity; known as Complex Instruction Set Computer (CISC). Such processors as the Intel 80286™ microprocessor, available from Intel Corp. of Santa Clara, Calif., belong to the CISC category of processor.
Previous computer system architecture has been optimized to take advantage of the CISC concept. Such systems typically have data buses thirty-two bits wide. However, applications targeted at computer supported cooperation (CSC—the integration of teleconferencing with mixed media data manipulation), 2D/3D graphics, image processing, video compression/decompression, recognition algorithms and audio manipulation increase the need for improved performance. But, increasing the execution speed and complexity of instructions is only one solution.
One common aspect of these applications is that they often manipulate large amounts of data where only a few bits are important. That is, data whose relevant bits are represented in much fewer bits than the size of the data bus. For example, processors execute many operations on eight bit and sixteen bit data (e.g., pixel color components in a video image) but have much wider data busses and registers. Thus, a processor having a thirty-two bit data bus and registers, and executing one of these algorithms, can waste up to seventy-five percent of its data processing, carrying and storage capacity because only the first eight bits of data are important.
As such, what is desired is a processor that increases performance by more efficiently using the difference between the number of bits required to represent the data to be manipulated and the actual data carrying and storage capacity of the processor.


REFERENCES:
patent: 3711692 (1973-01-01), Batcher
patent: 3723715 (1973-03-01), Chen et al.
patent: 4139899 (1979-02-01), Tulpule et al.
patent: 4161784 (1979-07-01), Cushing et al.
patent: 4393468 (1983-07-01), New
patent: 4418383 (1983-11-01), Doyle et al.
patent: 4498177 (1985-02-01), Larson
patent: 4707800 (1987-11-01), Montrone et al.
patent: 4771379 (1988-09-01), Ando et al.
patent: 4903228 (1990-02-01), Gregoire et al.
patent: 4963867 (1990-10-01), Bertrand
patent: 4989168 (1991-01-01), Kuroda et al.
patent: 5081698 (1992-01-01), Kohn
patent: 5095457 (1992-03-01), Jeong
patent: 5168571 (1992-12-01), Hoover et al.
patent: 5187679 (1993-02-01), Vassiliadis et al.
patent: 5237701 (1993-08-01), Bertrand
patent: 5268995 (1993-12-01), Diefendorff et al.
patent: 5390135 (1995-02-01), Lee et al.
patent: 5408670 (1995-04-01), Davies
patent: 5416731 (1995-05-01), Dang et al.
patent: 5423010 (1995-06-01), Mizukami
patent: 5426783 (1995-06-01), Norrie et al.
patent: 5465374 (1995-11-01), Dinkjian et al.
patent: 5477543 (1995-12-01), Purcell
patent: 5481746 (1996-01-01), Schiffleger et al.
patent: 5487159 (1996-01-01), Byers et al.
patent: 5553010 (1996-09-01), Tanihira et al.
patent: 5594437 (1997-01-01), O'Malley
patent: 5625374 (1997-04-01), Turkowski
patent: 5666298 (1997-09-01), Peleg et al.
patent: 5680161 (1997-10-01), Lehman et al.
patent: 5781457 (1998-07-01), Cohen et al.
patent: 5818739 (1998-10-01), Peleg et al.
patent: 5831877 (1998-11-01), Thompson
patent: 5848286 (1998-12-01), Schiffleger et al.
patent: 6098087 (2000-08-01), Lemay
patent: 6098162 (2000-08-01), Schiffleger et al.
patent: 6629115 (2003-09-01), Rossignol
patent: 6631389 (2003-10-01), Lin et al.
patent: 2001/0016861 (2001-08-01), Lin et al.
Case, B., “Philips Hopes to Displace DSPs with VLIW, TriMedia Processors Aimed at Future Multimedia Embedded Apps,” Microprocessor Report, Dec. 1994, pp. 12-18.
Errata to MC88110 Second Generation RISC Microproscessor User's Manual, Motorola, Inc., 1992, pp. 1-11.
Gwennap, L., “New PA-RISC Processor Decodes MPEG Video, H”'s PA-7100LC Uses New Instructions to Eliminate Decoder Chip, Microprocessor Report, Jan. 1994, pp. 16-17.
i860 TM. Microprocessor Family Programmer's Reference Manual, Intel Corporation, 1992, Chapters 1, 3, 8, and 12.
Intel i750, i860 TM, i960 Processor and Related Products, 1993, pp. 1-3.
Kawakami, Y., et al., “A Single-Chip Digital Signal Processor for Voiceband Applications,” IEEE, 1980 International Solid-State Circuits Conference, pp. 40-41.
Lee, R.B., “Accelerating Multimedia with Enhanced Microporcessors,” IEEE Micro, Apr. 1995, pp. 22-32.
Margulis, N., “i860 Microprocessor Architecture,” McGraw Hill, Inc., 1990, Chapters 6, 7, 8, 10, and 11.
MC88110 Programmer's Reference Guide, Motorola, Inc., 1992, pp. 1-4.
MC88110 Second Generation-RISC Microprocessor User's Manual, Motorola, Inc., Sep. 1992, pp. 1-1 through 2-23, pp. 2-1 through 2-20, 3-1 through 3-32, 5-1 through 5-25, 10-62 through 10-71, Index 1 through 17.
Motorola MC88110 Second Generation RISC Microprocessor User's Manual, Motorola, Inc., 1991.
Pentium Processor's User's Manual, vol. 3: Architecture and Programming Manual, Intel Corporation, 1993, Chapters 1, 3, 4, 6, 8, and 18.
Shipnes, J., “Graphics Processing with the 88110 RISC Microprocessor,” Motorola, Inc., IEEE, No. 0-8186-26455-0/92, 1992, pp. 169-174.
TMS320c2X, User's Guide, Digital Signal Processing Products, Texas Instruments, 1993, pp. 3-2-3-11; 3-28-3-34; 4-1-4-22; 4-41; 4-103; 4-119; 4-120; 4-122; 4-150; 4-151.
UltraSPARC Multimedia Capabilities On-Chip Support for Real0-Time Video and Advanced Graphics; SPARC Technology Business, Sep. 1994, Sun Microsystems, Inc.

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