Method of making integrated circuit structure with vertical isol

Fishing – trapping – and vermin destroying

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

437 62, 437 26, H01L 21265

Patent

active

055082114

ABSTRACT:
An integrated circuit structure vertically isolated electrically from the underlying substrate is formed in/on a single crystal semiconductor substrate, such as a silicon semiconductor wafer, by first implanting the substrate with a sufficient dosage of noble gas atoms to inhibit subsequent recrystallization of the semiconductor lattice in the implanted region during subsequent annealing, resulting in the formation of an isolation layer comprising implanted noble gas atoms enmeshed with semiconductor atoms in the substrate which has sufficient resistivity to act as an isolation layer. The preferred noble gases used to form such isolation layers are neon, argon, krypton, and xenon. When neon atoms are implanted, the minimum dosage should be at least about 6.times.10.sup.15 neon atoms/cm.sup.2 to inhibit subsequent recrystallization of the silicon substrate. When argon atoms are implanted, the minimum dosage should be at least about 2.times.10.sup.15 argon atoms/cm.sup.2. When krypton is implanted, the minimum dosage should be at least about 6.times.10.sup.24 krypton atoms/cm.sup.2. The energy used for the implant should be sufficient to provide an average implant depth sufficient to form, after annealing, the noble gas isolation layer at a depth of at least about 0.5 microns from the surface.

REFERENCES:
patent: 3622382 (1971-11-01), Brack
patent: 3663308 (1972-05-01), Davey
patent: 4053925 (1977-10-01), Burr et al.
patent: 5049521 (1991-09-01), Belanger et al.
patent: 5198371 (1993-03-01), Li
patent: 5334283 (1994-08-01), Parikh et al.
patent: 5399507 (1995-03-01), Sun
patent: 5441900 (1995-08-01), Bulucea et al.
Aronowitz, Sheldon, "Quantum-Chemical Modeling of Boron and Noble Gas Dopants in Silicon", J. Appl. Phys., vol. 54, No. 7, Jul. 1983, pp. 3930-3934.
Cullis, A. G., "Comparative Study of Annealed Neon-, Argon-, and Krypton-Ion Implantation Damage in Silicon", J. Appl. Phys., vol. 49, No. 10, Oct. 1978, pp. 5188-5198.
Revesz, P., et al., "Epitaxial Regrowth of Ar-Implanted Amorphous Silicon", J. Appl. Phys., vol. 49, No. 10, Oct. 1978, pp. 5199-5206.
Wittmer, M., et al., "Epitaxial Regrowth of Ne- and Kr-Implanted Amorphous Silicon", J. Appl. Phys., vol. 49, No. 10, Oct. 1978, pp. 5207-5212.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of making integrated circuit structure with vertical isol does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of making integrated circuit structure with vertical isol, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making integrated circuit structure with vertical isol will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-324757

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.