Abrading – Abrading process – Glass or stone abrading
Reexamination Certificate
2000-04-21
2004-04-27
Hail, III, Joseph J. (Department: 3723)
Abrading
Abrading process
Glass or stone abrading
C451S365000, C269S071000
Reexamination Certificate
active
06726537
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to a semiconductor wafer polishing apparatus and, more specifically, to a semiconductor wafer carrier that is capable of grasping the edge of the semiconductor wafer during a chemical/mechanical polishing process.
BACKGROUND OF THE INVENTION
Conventional chemical/mechanical polishing (CMP) has been developed for providing smooth topographies of the various layers formed during semiconductor device manufacture. The CMP process involves holding, and rotating, a thin, reasonably flat, semiconductor wafer against a rotating polishing platen. The wafer may be repositioned radially within a set range on the polishing platen as the platen is rotated. The polishing surface, which is conventionally an open-celled, polyurethane pad affixed to the polishing platen, is wetted by a chemical slurry, under controlled chemical, pressure, and temperature conditions. The chemical slurry contains selected chemicals which etch or oxidize selected surfaces of the wafer during CMP in preparation for their mechanical removal. The slurry also contains a polishing agent, such as alumina or silica, that is used as the abrasive material for the physical removal of the etched/oxidized material. The combination of chemical and mechanical removal of material during polishing results in superior planarization of the polished surface. In this process it is important to remove a sufficient amount of material to provide a smooth surface, without removing an excessive amount of underlying materials at each level of the manufacturing process to insure uniform and accurate formation of the semiconductor device at all subsequent levels. Accurate material removal is particularly important in today's sub-quarter micron technologies where it is critical to minimize thickness variation because the metal lines are getting thinner.
The semiconductor wafer is typically transported to the polishing platen by applying a vacuum against the back of the wafer through the carrier head. This holds the wafer in the carrier head and the vacuum is continually applied until the wafer is placed on the polishing pad. While this system does work well in most instances, the vacuum applied to the wafer can sometimes lead to wafer breakage. When this occurs, fragments of the wafer and slurry can find their way into the vacuum system, which can cause the vacuum system to malfunction. In such instances, the apparatus must be taken off line for cleaning and repair. This, of course, causes delays in the manufacturing process. In addition the wafer breakage can lead to increased overall fabrication costs.
Another problem arises with a conventional polishing apparatus in that once the wafer is positioned on the polishing pad, the wafer is allowed to “free float” within the confines of the carrier ring during the polishing process. Due to allowable variations in the diameter of semiconductor wafers, a small diameter wafer may then move around somewhat within the carrier ring. This causes the center of the semiconductor wafer to be non-aligned to the centerline of the carrier head during polishing. As a result, the wafer surface may develop irregular topographies on the surface being polished, which is highly undesirable.
Accordingly, what is needed in the art is an apparatus that avoids the deficiencies of the prior art for semiconductor wafer CMP.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention provides a method for manufacturing an integrated circuit using a polishing head in a polishing apparatus. In one advantageous embodiment, the polishing head comprises a wafer carrier having an outer periphery and a wafer holder. The wafer holder is coupled to the wafer carrier and depends from the outer periphery thereof. The wafer holder is configured (i.e., designed) to grip an edge of the semiconductor wafer.
Thus in one aspect, the present invention provides a semiconductor wafer carrier that comprises a wafer holder configured to grip the semiconductor wafer by its edge for chemical/mechanical polishing; that is, the wafer holder has an overall design that allows it to grip the wafer, versus holding the wafer by only a vacuum. This configuration provides a more continuous connection between the semiconductor wafer edge and the wafer holder, thereby minimizing the opportunity for slurry to migrate to the back side of the wafer and canting of the wafer in the carrier head.
In one embodiment, the wafer holder comprises a collet configured to contract about the wafer edge such that it can grip a fabrication wafer. In an alternative embodiment, the collet comprises an annular band configured to contract about its edge. In one particular aspect of this embodiment, the collet comprises arcuate segments configured to contract radially about its edge. In a related embodiment, the polishing head further comprises guides coupled to the arcuate segments and are configured to guide the arcuate segments as the arcuate segments contract radially about the edge.
In an embodiment to be illustrated and described, the polishing head further comprises an annulus coupled to the wafer carrier and to the arcuate segments with the annulus depending from the outer periphery. The polishing head may further comprise a contraction device coupled to the wafer holder and that is configured to exert a contraction force on the wafer holder. The wafer holder may be operated, for example, by a vacuum, pneumatic, hydraulic, mechanical, or electrical power source.
The wafer carrier, in yet another embodiment, further comprises an inner face and depth sensors. The depth sensors are configured to position the inner face at a prescribed distance from a surface of the semiconductor wafer that opposes the inner face. The depth sensors may be designed to be retractable into the inner face. In another embodiment, the wafer carrier further includes a wafer polishing film interposed the semiconductor wafer and the wafer carrier.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
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Crevasse Annette M.
Easter William G.
Maze John A.
Miceli Frank
Agere Systems Inc.
Hail III Joseph J.
Ojini Anthony
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