Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2003-03-20
2004-07-27
Nguyen, Long (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S112000, C326S081000
Reexamination Certificate
active
06768368
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to level shifter circuits, and more particularly to a level shifter circuit in a large scale integrated circuit (LSI), having multiple circuit blocks operating at different power supply voltages, the level shifter circuit translating a signal from a lower power supply voltage to a higher power supply voltage.
BACKGROUND OF THE INVENTION
A large scale integrated circuit (LSI) can include a single integrated circuit (e.g., a chip) having one logic circuit system adapted to operate with a high voltage power source, and another logic circuit system adapted to operate with a low voltage power source. Such an LSI can include a level shifter circuit that operates with the high voltage power source. The level shifter circuit converts an output signal from the lower voltage operating circuit system to a higher level for use in the higher voltage operating circuit system and/or for output via an external pin, or the like.
In an LSI having a number of blocks adapted to operate with different voltage power sources, like that described above, power consumption can be reduced by turning off (powering down) particular voltage power sources when the corresponding blocks are not in operation. Drawbacks can arise in such arrangements when a voltage power source is turned off. In particular, when a lower voltage power source is turned off, input signals for a level shifter circuit can become indeterminate. Such indeterminate input values can result in a leakage current flowing through an inverter within a level shifter circuit. Such a leakage current results in wasteful power consumption.
One conventional approach to addressing the above problem is shown in Japanese Patent Publication 9-74348A (hereinafter JP 9-74348A). JP 9-74348A shows an arrangement in which a level shifter circuit can be placed in an off state when a low voltage power source is turned off. This can prevent a current from flowing through the level shifter circuit when a low voltage power source is in the “power-down” state, thereby reducing power consumption.
FIG. 3
is a schematic diagram of a conventional level shifter circuit having the above-mentioned power down function. In
FIG. 3
, a terminal
1
can be an input terminal that receives an output signal from a low voltage system circuit. A terminal
2
can be a control terminal that receives a high voltage level when a low voltage power source is on and a ground voltage level when the low power voltage source is off. A terminal
3
can be an output terminal that provides a level shifted output signal. An input signal at a terminal
1
can be received by a level shifter unit
12
directly or through an inverter
10
operating at the low voltage power source. An output signal that is level shifted by a level shifter unit
12
can be supplied to terminal
3
by an inverter
11
. An inverter
11
operates at the high voltage power source.
The conventional level shifter unit
12
includes p-channel metal-oxide-semiconductor (PMOS) transistors
4
and
5
and n-channel MOS (NMOS) transistors
7
and
8
. PMOS transistors
4
and
5
have source electrodes connected to a high voltage power source and gate electrodes connected in a cross-coupled fashion to their respective drains. NMOS transistors
7
and
8
have gate electrodes that receive an output of inverter
10
and terminal
1
, respectively, drain electrodes connected to the drains of PMOS transistors
4
and
5
, respectively, and commonly connected source electrodes. A signal obtained by level shifting can be output at the drain electrodes of commonly connected PMOS transistor
5
and NMOS transistor
8
.
In order to provide sufficient drive capacity, a channel width of a PMOS transistor
5
connected to an output side of level shifter unit
12
can be larger than that of PMOS transistor
4
connected to an input side of the level shifter unit
12
.
The arrangement of
FIG. 3
also includes an NMOS transistor
9
having a source-drain path connected between the commonly connected sources of NMOS transistors
7
and
8
and a ground potential. When a low voltage power source is on, a terminal
2
can receive a high voltage level that is applied to a gate of NMOS transistor
9
. NMOS transistor
9
can turn on and bring level shifter unit
12
into an operational state. When a low voltage power source is off, a terminal
2
can receive a low voltage level that is applied to a gate of NMOS transistor
9
. NMOS transistor
9
can turn off to stop the operation of level shifter unit
12
.
In addition, a PMOS transistor
6
can be included that has a source-drain path connected between the output terminal of level shifter unit
12
and a high voltage power source. PMOS transistor
6
can provide a “pull-up” operation. As noted above, when the low voltage power source is on, a terminal
2
can receive a high voltage level that is applied to a gate of PMOS transistor
6
, and PMOS transistor
6
can be turned off. In contrast, when the low voltage power source is off, a terminal
2
can receive a low voltage level that is applied to a gate of PMOS transistor
6
. PMOS transistor
6
can turn on, thereby pulling the output terminal of level shifter
12
to a high voltage level. The operation of inverter
11
can fix the output terminal
3
at a low level.
As has been shown above, the level shifter circuit having the power down function of
FIG. 3
includes inverters
10
and
11
, level shifter unit
12
, NMOS transistor
9
for controlling the operation of the level shifter unit
12
, and PMOS transistor
6
for pulling the level of the output terminal of the level shifter unit
12
to a high voltage level when the level shifter unit
12
is in a non-operation state. In this configuration, when a low voltage power source is off, because NMOS transistor
9
is turned off, level shifter unit
12
can be placed in a non-operation state, thereby preventing current from flowing through the level shifter unit
12
. In addition, PMOS transistor
6
is turned on, causing the output of level shifter unit
12
to go to a high level, which fixes the level of output terminal
3
at a low level.
As the scale of an LSI increases, the number of terminals that are to be connected to an external circuit can also increase. Consequently, the number of pins required for external connections for an LSI can increase correspondingly. Such increases in pin count can undesirably increase LSI package size, cost, or the like. In order to avoid unduly increasing the pin count of an LSI device, specifications are proposed in which output pins are shared among multiple blocks of an LSI by a mode switching operation. For example, an LSI device may include 224 pins, but 60 such pins are shared.
In devices like that described above, which include multiple blocks operating at different voltage power source levels and shared common output terminals, a level shifter is used in an input/output (I/O) buffer. In addition, it is also desirable to provide power-down modes for such devices. In a power-down mode, a block that does not output a signal to I/O buffer can be turned off.
FIG. 4
is a block schematic diagram showing an example of an LSI configured according to the above specifications.
Referring now to
FIG. 4
, an LSI
400
can include a low voltage system block
401
adapted to operate with a low voltage power source (e.g., 2.5 volts), a high voltage system block
404
adapted to operate with a high voltage power source (e.g., 3.5 volts), and an I/O buffer
405
that has a level shifter circuit and a signal selector circuit. Output signals from a low voltage system block
401
, output signals from a high voltage system block
404
, and a power-down mode switching signal from a terminal
402
can be input to I/O buffer
405
. I/O buffer
405
can output signals from high voltage system block
404
through terminals
403
when high voltage system block
404
is in operation. I/O buffer
405
can also level shift output signals from low voltage system block
401
, and output the resulting level shifted
Kaneko Tomohiro
Tozawa Kazuo
NEC Electronics Corporation
Nguyen Long
Sako Bradley T.
Walker Darryl G.
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