Margining pin interface and control circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

Reexamination Certificate

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Details

C327S333000

Reexamination Certificate

active

06798260

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to voltage level control circuits, and is particularly directed to a voltage margin setting interface circuit having a single input pin, and being capable of programming a reference voltage level, such as may be supplied to an error amplifier of a voltage regulator circuit of the power supply of a personal computer.
BACKGROUND OF THE INVENTION
The technique of varying the voltage to various controller integrated circuits is termed ‘power margining’. This technique has become increasingly important for the portable computer market, where the processor voltage is controllably increased depending upon operational demands. For example, the power may be decreased during low processing requirements, to result in a reduction in standby power. In a complementary manner, when there is a need for faster signal processing, for example, in graphics processing applications, processor speed must be increased to handle rapid or complex display changes. Associated with this increase in processor speed, the supply voltage is also increased to accommodate temporary high performance and power demands. On the other hand, when there is no need for speed, the power to the processor is reduced by way of a lower processor voltage, resulting in improved power supply economy.
SUMMARY OF THE INVENTION
With this objective in mind, the present invention is directed to a new and improved power margining interface, configured to provide on-demand adjustment of a reference voltage by way of a single input pin. For this purpose, a current direction control circuit is coupled between a single input pin and an output port from which a controllably adjustable reference voltage is to be derived. In response to a first input current state, the current direction control circuit causes a prescribed current to flow in a first direction through an output resistor that is coupled to the output port, so as to increase the output voltage relative to a prescribed reference voltage. Conversely, in response to a second input current state, the current direction control circuit causes a prescribed current to flow in a second direction through the output resistor, so as to decrease the output voltage relative to the prescribed reference voltage.
The current direction control circuit is implemented by coupling the control or input voltage through an input resistor to a single operational amplifier, which is referenced to a voltage midway between the voltage range of the input voltage and having its output coupled to a pair of complementary polarity transistors, operating in their linear range. These transistors have their current flow paths coupled in series to the drive inputs of a first pair of current mirror amplifier stages, referenced to opposite polarity voltages.
The first pair of current mirror amplifiers have their mirrored current outputs cross-coupled to inputs of a second pair of current mirror amplifiers, whose mirrored current outputs are coupled to a common output node. This output node is coupled through a series resistor to a voltage reference terminal to which a prescribed reference voltage, such as that supplied by a digital-to-analog converter may be supplied. The output node may be coupled to an error amplifier of a voltage regulator circuit of a personal computer power supply, as described above. Variations in input current and thereby the voltage input to the operational amplifier relative to its reference voltage are used to adjust the current mirrored current through the series output resistor, so as to increase or decrease the output reference voltage.


REFERENCES:
patent: 5508650 (1996-04-01), Grimm et al.
patent: 6111469 (2000-08-01), Adachi
patent: 6286127 (2001-09-01), King et al.
patent: 6424211 (2002-07-01), Nolan et al.

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