Non-volatile semiconductor memory device with cache function...

Details Non-volatile semiconductor memory device with cache function... Non-volatile semiconductor memory device with cache function...

2002-10-23

2004-04-06

Tran, Michael (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185170

Reexamination Certificate

active

06717857

ABSTRACT:

RELATED APPLICATION
This application claims priority from Korean Patent Application No. 2001-65766, filed on Oct. 24, 2001, the contents of which are herein incorporated by reference in their entirety.
FIELD OF THE INVENTION
This disclosure relates to data storage devices and, more particularly, to a device for writing/reading data to/from a memory cell.
BACKGROUND OF THE INVENTION
Semiconductor memory devices are typically classified into volatile memory devices and non-volatile memory devices. The volatile memory devices are subdivided into dynamic random access memories (DRAMs) and static random access memories (SRAMs). The volatile semiconductor devices read/write data at high speed, but lose their data when their power supplies are interrupted. The non-volatile memory can include mask read-only memories (MROMs), programmable read-only memories (PROMs), erasable programmable read-only memories (EPROMs), and electrically erasable programmable read-only memories (EEPROMs). The non-volatile memory devices retain their stored data even when their power supplies are interrupted. Thus, the non-volatile memories are widely used to store retention-required data irrespective of power supply interruption.
However, MROMs, PROMs, and EPROMs have difficulty in rewriting stored data because read and write operations cannot be freely conducted by normal users. On the other hand, EEPROMs are increasingly used in system programming that requires the continuous update or auxiliary memory devices. Particularly, flash EEPROMs are very advantageous to be used as mass storage devices because their integration density is high as compared to conventional EEPROMs. Among the flash EEPROMs, a NAND-type flash EEPROM has a very high integration density as compared to a NOR-type or AND-type flash EEPROM.
A flash EEPROM includes a memory cell array as a data storage area. Referring to
FIG. 1
, a memory cell array
10
has a plurality of cell strings (or NAND strings) each being respectively coupled to corresponding bitlines. Each of the cell strings
12
includes a string selecting transistor SST coupled to a corresponding bitline (e.g., BL
0
), a ground selecting transistor GST coupled to a common source line CSL, and memory cells MC
0
-MCm serially coupled between the string and ground selecting transistors SST and GST. The string selecting transistor SST, the memory cells MC
0
-MCm, and the ground selecting transistors GST are coupled to a string selecting line SSL, wordlines WL
0
-WLm, and a ground selecting line GSL, respectively. The lines SSL, WL
0
-WLm, and GSL are electrically connected to a row decoder circuit
12
. Bitlines BL
0
-BLn are electrically connected to a page buffer circuit
14
.
Each of memory cells constituting respective cell strings includes a floating gate transistor having a source, a drain, a floating gate, and a control gate. It is well known that a memory cell of a NAND-type flash EEPROM is erased and programmed using F-N (Fowler-Nordheim) tunneling current. Methods of erasing and programming a NAND-type flash EEPROM are disclosed in, for instance, U.S. Pat. No. 5,473,563 entitled “NONVOLATILE SEMICONDUCTOR MEMORY”, and U.S. Pat. No. 5,696,717 entitled “NONVOLATILE INTEGRATED CIRCUIT MEMORY DEVICE HAVING ADJUSTABLE ERASE/PROGRAM THRESHOLD VERIFICATION CAPABILITY”.
In order to store data in a memory cell array, a data loading command is applied to a flash EEPROM, and then an address and data are inputted thereto. Generally, data to be programmed are sequentially transferred to a page buffer circuit by a byte or word unit. When the data to be programmed, i.e., a page of data are all loaded to the page buffer circuit, the data stored in the page buffer circuit are programmed to a memory cell array at the same time.
In case of a NAND-type flash EEPROM, it takes about 200-500 microseconds to program 512-bytes of data information, for example. It takes about 100 nanoseconds to load byte or word data into a page buffer circuit. Therefore, it takes approximately 50 microseconds to load all 512-bytes of data information into the page buffer circuit (i.e., data load time is approximately 50 microseconds). Total program time Ttotal_PGM is defined as (tLOAD+tPROGRAM)×N (wherein tLOAD, tPROGRAM, and N represent data load time, practical program time, and the number of program cycles, respectively). In a case where program operations are successively carried out, the data load time tLOAD occupies a sizable proportion of the total program time tTOTAL_PGM. This entails considerable difficulty in constructing a high-speed NAND-type flash EEPROM.
In a case where a page size is increased, the data load time tLOAD is increased in proportion to the increased page size, while keeping the practical program time tPROGRAM. In a case where program operations are successively carried out, the total program time tTOTAL_PGM is considerably increased. This is because the next data to be programmed in the NAND-type flash EEPROMcan be loaded to a page buffer circuit only after completely programming previously loaded data. Thus, an increase in the total program time tTOTAL_PGM has an influence upon data storage characteristics of the NAND-type flash EEPROM. For example, a program speed of the NAND-type flash EEPROM is greatly reduced with increase in the page size.
The NAND-type flash EEPROM supports a page copy-back operation, which means data information can be copied from one page to another page without being output to an exterior. One example of a NAND-type flash EEPROM supporting the copy-back operation is disclosed in U.S. Pat. No. 5,996,041 entitled “INTEGRATED CIRCUIT MEMORY DEVICES HAVING PAGE FLAG CELLS WHICH INDICATE THE TRUE OR NON-TRUE STATE OF PAGE DATA THEREIN AND METHOD OF OPERATING THE SAME”, which is incorporated herein by reference for all purposes. According to the above reference, a page copy flag cell is provided for storing information to detect whether the copied page data is inverted. That is, a flag cell string
16
coupled to a flag bitline FBL is further provided to a memory cell array
10
, as shown in FIG.
1
. Substantially, the flag cell string
16
has the same construction as other cell strings
12
.
If there is a defect in a page copy flag cell, page data of the defective page copy flag cell cannot be guaranteed. Even though memory cells substantially constructing a page are normal, normal page data cannot be guaranteed due to the defective flag cell belonging to the page. As a result, a page copy flag cell provided for a page copy-back operation becomes an obstruction in securing a reliability of the NAND-type flash EEPROM. Moreover, when data information is read out from a selected page, there is a need for an additional circuit (see
FIG. 4
of U.S. Pat. No. 5,996,041; XOR gates) that allows the data information to be outputted as its inverted version or in its entirety.
Embodiments of the invention address this and other limitations of the prior art.
SUMMARY OF THE INVENTION
Embodiments of the present invention provide a flash memory device having a page buffer circuit with a cache function.
These embodiments can perform a copy-back operation without the need for a separate copy flag cell.
Further embodiments of the present invention provide a flash memory device that prevents the deterioration of a data storage characteristic, and can enhance read and program operation speeds.


REFERENCES:
patent: 5473563 (1995-12-01), Suh et al.
patent: 5696717 (1997-12-01), Koh
patent: 5996041 (1999-11-01), Kim
patent: 6104640 (2000-08-01), Banks

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