Static information storage and retrieval – Floating gate
Reexamination Certificate
2002-10-30
2004-07-06
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Floating gate
C365S185100
Reexamination Certificate
active
06760252
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a floating gate memory cell for nonvolatile information storage, a semiconductor memory device having a plurality of memory cells for nonvolatile information storage, and a method for fabricating a floating gate memory cell for nonvolatile information storage.
In the further development of semiconductor memory devices based upon nonvolatile memory mechanisms, the principle of the so-called nonvolatile floating gate memory cell has also been developed. Such a floating gate memory cell for nonvolatile information storage has a floating gate configuration, a source/drain configuration, and a control gate configuration. The floating gate configuration serves for the actual information storage, while the source/drain configuration is configured for access to the floating gate configuration and, thus, for access to the respective information. The control gate configuration is configured for controlling such access to the floating gate configuration and to the information.
What is disadvantageous in the case of existing semiconductor memory devices, memory cells contained therein, and corresponding fabrication methods for semiconductor memory devices or memory cells is that their fundamental concept, from a structural and production engineering standpoint, is based on the provision of a single binary information unit in each individual memory cell. Each memory cell and, thus, each memory location are, thus, occupied only singularly with information and configured accordingly.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a floating gate memory cell, method for fabricating it and semiconductor memory device that overcome the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that, in a particularly simple manner, obtains a particularly high information density and, in a particularly reliable manner, modifies and retrieves such information.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a floating gate memory cell for nonvolatile storage of information including at least one of information units and binary bits, including a floating gate configuration for storing the information, the floating gate configuration having floating gates each independently storing the information and, as a result, storing a corresponding plurality of one of the information units and the binary bits independently of one another in the memory cell, a source/drain configuration accessing the floating gate configuration, a control gate configuration controlling access to the floating gate configuration, the control gate configuration having control gates each associated with a respective one of the floating gates, access to the respective one of the floating gates being controlled by each respective one of the control gates, and the source/drain configuration having two source/drain regions jointly provided for the floating gates and the control gates to permit access of all of the floating gates through the two common source/drain regions.
The invention's floating gate memory cell for nonvolatile information storage is characterized in that the floating gate configuration has a plurality of floating gates, in that each of the floating gates is configured for substantially independent information storage, and in that, as a result a corresponding plurality of information units, in particular, binary bits, can be stored independently in the memory cell.
Thus, in contrast to the prior art, the invention departs from the one-bit concept and, consequently, the floating gate memory cell according to the invention is configured for storing a plurality of information units, in particular, binary bits or the like. Such a characteristic is realized by virtue of the fact that, in contrast to the floating gate memory cell according to the prior art, the floating gate configuration is configured with a plurality of floating gates. In such a case, each of the floating gates is configured for separate and independent information storage independently of the other floating gates. Consequently, by way of example, a respective bit can be written and retrieved, in accordance with an impressed potential state, in each of the floating gates.
Each floating gate can also be configured for taking up more than two charge and/or potential states, thereby, further increasing the information density per floating gate memory cell.
The structure of the floating gate memory cell according to the invention is configured particularly flexibly if, in accordance with another feature of the invention, the control gate configuration has a plurality of control gates, a respective control gate is assigned to a respective floating gate and the access to the assigned floating gate and the information state contained therein is controllable by each control gate. The initially organizational assignment of a respective control gate of the control gate configuration with a respective floating gate of the floating gate configuration results in a particularly flexible control of the access to the information to be stored in the floating gate. The initially organizational and sequence-technical assignment between floating gate and control gate will, advantageously, also be represented in a structural or spatial assignment, in particular, in a particular spatial proximity of the assigned floating gates and control gates with respect to one another.
A further simplification of the floating gate memory cell according to the invention results if the source/drain configuration has two source/drain regions, the source/drain regions are provided jointly for the plurality of floating gates and/or for the plurality of control gates, and all the floating gates can be accessed by the two common source/drain regions.
With regard to a particularly simple fabrication procedure and also with regard to a corresponding functional reliability, the floating gates are configured substantially identically with regard to their geometrical and/or material properties.
For the reliability of the floating gate memory cell according to the invention, on the other hand, the floating gates are disposed and configured in a manner substantially electrically insulated from one another, from the control gates and from the source/drain regions, and in that, in particular, each floating gate in the floating gate memory cell is configured and disposed in a substantially capacitively coupled manner.
Furthermore, it is advantageous that the floating gates are configured substantially identically with regard to their geometrical and/or material properties.
It is further preferred that the control gates are disposed and configured in a manner substantially electrically insulated from one another, from the floating gates, and from the source/drain regions.
In accordance with a further feature of the invention, the floating gates and/or the control gates are composed of a polysilicon material, polycide, metal, and/or the like.
In accordance with an added feature of the invention, the floating gates and the control gates are composed substantially of the same material.
To realize the assignment between the floating gates and the control gates, in accordance with an additional feature of the invention, the mutually assigned floating gates and control gates are in each case configured in direct spatial proximity to one another, and that, in particular, respective intermediate insulation regions are provided in such a case, in particular, in each case an intermediate dielectric between the respectively assigned floating gates and the control gate.
The intermediate dielectric is also referred to as interpoly dielectric and may be, e.g., an NO or ONO structure, i.e., a structure with a configuration including nitride/oxide or oxide
itride/oxide, respectively.
It is, furthermore, preferred that each floating gate has a first end region and a second end region. The respective first end r
Greenberg Laurence A.
Infineon - Technologies AG
Lebentritt Michael S.
Luu Pho M.
Mayback Gregory L.
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