Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2002-05-02
2004-09-14
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
With measuring or testing
C438S011000, C438S018000
Reexamination Certificate
active
06790685
ABSTRACT:
BACKGROUND
1. Technical Field
A method of forming a test pattern in a semiconductor device is disclosed, and, more specifically a method of forming a test pattern in a semiconductor device which can identify overetch and underetch that occur side walls of a pattern after an etching process is disclosed.
2. Description of the Related Art
In general, overetch or underetch may occurs at side walls of a gate electrode during the formation of the gate electrode through an etching process. Due to the overetch or underetch, channel length or channel width is changed, thereby deteriorating the electric characteristic of a semiconductor device. It is therefore desirable to measuring variation of the electric characteristic by monitoring an etching profile of the side walls of the gate electrode after the formation of the gate electrode. In a polysilicon and metal stacked gate structure that has being broadly used in logic and DRAM devices, it is difficult to monitor an etching profile of side walls of an under polysilicon gate which affects electric characteristic of the device.
FIG. 1
illustrates a sectional view for explaining structure of a transistor. A transistor having a gate, a source and a drain is formed on a semiconductor substrate, in which a field oxide film
12
and a well
13
are formed. The gate having a gate oxide film
14
, a polysilicon film
15
, a barrier metal film
16
and a metal film
17
, which are sequentially stacked, is formed on the well
13
and a spacer
18
is then formed on side walls of the gate. A source and a drain are formed in the semiconductor substrate
11
by means of an impurity ion implant process.
During an etching process for the gate after sequentially forming the gate oxide film
14
, the polysilicon film
15
, the barrier metal film
16
and the metal film
17
, overetch or underetch may be occurred the side wall A of the polysilicon film
15
. As shown in
FIG. 1
, due to the occurrence of the overetch or the underetch in the side wall A of the polysilicon film
15
, a channel length is changed and thereby deteriorating electric characteristic.
As a matter of fact,
FIG. 1
illustrates a typical sectional view of a transistor having a metal and polysilicon stacked gate structure and illustrates an enlarged sectional view of “A” portion. In a metal and polysilicon stacked gate structure, the polysilicon film may be over etched due to the difference of etching selectivity between the metal, for example tungsten, and the polysilicon film, as shown in FIG.
1
. It is impossible to monitor such an overetch by a conventional SEM equipment for In-line monitor. Such an overetch can be monitored by using a TEM photograph. However, it is difficult to monitor the overetch or under etch in all patterning process of a wafer.
SUMMARY OF THE DISCLOSURE
Therefore, methods of forming a test pattern in a semiconductor device are disclosed which solve the above problems.
A desired pattern is formed by means of a semiconductor process including an etching process and a current is then applied to the pattern. Voltage between first and second portions of the pattern is measured to obtain resistance and a cross sectional area of the pattern is calculated by using the resistance. That is, an etching profile of the under layer to which an etching process is performed is nondestructively and electrically measured with using the conventional MOSFET pattern as it is. It is possible to quantitatively analysis fluctuation of transistor characteristic, which is directly related to yield, due to change of a gate pattern.
A method of forming a test pattern according to the disclosure comprises:
forming first and second junction regions having a symmetrical structure on both side of field oxide layer formed on a semiconductor substrate;
forming third and fourth junction regions having a asymmetrical structure on front and rear portions of said field oxide layer;
forming a test pattern having first and second projection portions on said semiconductor substrate, in which both side portions of said test pattern are overlapped with said first and second junction regions and said first and second projection portions which are formed on front and rear portions of said test pattern are overlapped with said third and fourth junction regions;
forming an inter insulating layer on a resulting structure after forming said test pattern;
patterning said inter insulating layer to expose a portion of said first to fourth junction regions;
forming current supply lines connected to said first and second junction regions, respectively; and
forming voltage measuring lines connected to said third and fourth junction regions, respectively.
The test pattern is a stack structure having a polysilicon layer, an insulating layer and a metal layer and the polysilicon layer is formed by a process of forming a polysilicon layer for a gate of a transistor which is formed on a peripheral region of said semiconductor substrate.
Another method of forming a test pattern comprises:
defining an active region by forming a field oxide layer on a semiconductor;
forming a test pattern having projection regions on said semiconductor substrate to vertically cross with said active region, in which said projection regions are formed to cross from each other in center of said active region and said is not overlapped with said active region;
performing a thermal treatment after implanting an impurity ion to an exposed portion of said active region so that first and second impurity regions are formed, wherein first and second impurity regions are overlapped with both side portions of a conductive layer;
forming an inter insulating layer on a resulting structure after forming said first and second impurity regions;
patterning said inter insulating layer to expose both edges of said active region and a portion of said projection portions;
forming current supply lines connected to said edge portions of said active region, respectively; and
forming voltage measuring lines connected to said projection portions, respectively.
The step of forming a gate oxide layer may be performed after forming said field oxide layer.
The projection portion is narrower than a portion overlapped with said active region and have a “
” or “
” shape.
A method of measuring etching characteristic using a test pattern comprises:
supplying a current to said test pattern having first and second regions;
measuring voltage between said first and second regions; and
calculating a cross sectional area by resistance obtained by using said current and the measured voltage so that the etching characteristic of said test pattern is measured.
Another method of measuring etching characteristic using a test pattern comprises:
providing a test pattern formed by the method of the first embodiment;
supplying a current through said current supplying lines;
measuring voltage between said first and second region through said voltage measuring lines connected to said first and third projection portions; and
calculating a cross sectional area by resistance obtained by using said current and the measured voltage so that the etching characteristic of said test pattern is measured.
Another method of measuring etching characteristic using a test pattern comprises:
providing a test pattern formed by the method of the second embodiment;
supplying a current through said current supplying lines;
measuring voltage between said projection portions of said test pattern through said voltage measuring lines connected to said projection portions; and
calculating a cross sectional area by resistance obtained by using said current and the measured voltage so that the etching characteristic of said test pattern is measured.
Another method of measuring etching characteristic using a test pattern comprises:
providing a test pattern formed by the method of the second embodiment;
supplying a voltage through said voltage measuring lines to form a channel in said active region under said test pattern;
supplying a voltage to said first impurity region so that current flows from said first
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