Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By phase
Reexamination Certificate
2002-12-26
2004-03-16
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By phase
C327S043000
Reexamination Certificate
active
06707319
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a frequency comparator with a malfunction reduced at the time of performing frequency comparison on a data signal having large jitter, and a phase-locked state detecting circuit using the same.
2. Description of the Background Art
A circuit for comparing the frequency of an input signal from the outside of a chip with the frequency of an internal clock generated by an internal oscillator is called a frequency comparator. The frequency comparator outputs a control signal DOWN when the frequency of the internal clock is high and outputs a control signal UP when the frequency of the internal clock is low. The frequency comparator is used for a control of optimizing the frequency of the internal oscillator with respect to a signal input from the outside.
FIG. 16
is a circuit diagram showing the configuration of a conventional frequency comparator
500
.
Referring to
FIG. 16
, frequency comparator
500
is the same circuit as that described in a reference of Lawrence M. DeVito “A Versatile Clock Recovery Architecture and Monolithic Implementation”, pp. 405-420, Monolithic Phase Locked-Loops and Clock Recovery Circuits, edited by B. Razavi, IEEE Press. Frequency comparator
500
, shown in
FIG. 14
of the reference, compares input data with four clocks of phases which are different from each other by 90°, and outputs control signal UP or DOWN.
FIG. 17
is a diagram for explaining the operation of frequency comparator
500
of FIG.
16
.
Referring to
FIG. 17
, phases of rising edges of four-phase clocks are set to 0°, 90°, 180° and 270°, and a change point (hereinafter, also referred to as a data edge) of an input data signal DATA in a phase with respect to the clock is expressed by a position on a circle graph of 0° to 360°. A region in which the phase of the data edge lies in a range from 0° to 90° will be called a region A. A region in which the phase of the data edge lies in a range from 90° to 180° will be called a region B. A region in which the phase of the data edge lies in a range from 180° to 270° will be called a region C. A region in which the phase of the data edge lies in a range from 270° to 360° will be called a region D.
When the edge of data signal DATA changes from region B to region C within one clock, frequency comparator
500
outputs control signal DOWN.
On the contrary, when the edge of data signal DATA changes from region C to region B within one clock, frequency comparator
500
outputs control signal UP.
When the edge of data signal DATA is in region A or D, frequency comparator
500
outputs nothing.
When the phase of the data signal and that of the clock are the same, that is, in a phase-locked state, it can be considered that the edge of the data signal is in region A or D. In this state, the frequency comparator does not output control signals UP and DOWN, and it is considered that, in a clock recovery circuit which receives the control signal and determines the clock frequency, the condition of a constant frequency is maintained.
However, generally, fluctuations in timing, called jitter, at which data is switched exists in a data signal. Ideally, the data edge is positioned at 0° on the graph of FIG.
17
. However, in the case where jitter is ±90° or larger with respect to, for example, the phase of the clock, even in the phase-locked state, there is the possibility that the data edge is positioned in the region B or C. In such a case, it is feared that, depending on the condition, control signal UP or DOWN is erroneously output.
FIG. 18
is an operation waveform chart for explaining the state where jitter exists in data signal DATA.
Referring to
FIG. 18
, the rising edge of a clock signal ICLK is 0° and a clock signal QCLK rises behind the rising edge by the phase of 90°. Reference characters A, B, C, and D correspond to the regions A, B, C, and D of
FIG. 17
, respectively.
When data signal DATA is overwritten in certain cycles, an eye pattern is obtained. In the eye pattern in the phase-locked state, fluctuations in waveform due to jitter exist around the border between the regions D and A.
The waveform of one of data signals DATA having large jitter is shown below the eye pattern. Ideally, data signal DATA rises at time t
1
and falls at time t
4
. However, due to the large jitter, the rising edge of data signal DATA exists in region B after time t
2
, and the following falling edge exists in region C before time t
3
.
In such a case, since the data edge changes from region B to region C at time t
3
, a phase E
11
changes to a phase E
12
in
FIG. 17
, and frequency comparator
500
outputs control signal DOWN.
FIG. 19
is an operation waveform chart showing another case of erroneous operation.
FIG. 19
shows a case that when a data signal and a clock signal are phase-locked with a predetermined phase offset at two input nodes of a frequency comparator, for example, an average edge of the data signals lies in region C. In such a case, when the edge of data signal DATA in the following cycle lies in region B due to jitter, control signal UP is output. That is, the rising edge of data signal DATA at time t
1
is sampled in region C, and the falling edge of data signal DATA is sampled in region B at time t
2
. In such a case, control signal UP is output.
In conventional frequency comparator
500
the control signal is output in the case where the jitter of data signal DATA is large. Although an average clock frequency and an average data cycle are equal to each other, the control signal is output when the edge of data signal DATA instantaneously lies not in an inherently expected position.
Therefore, such an error of the frequency comparator with respect to a data signal having large jitter has to be solved.
SUMMARY OF THE INVENTION
An object of the invention is to provide a frequency comparator with a malfunction reduced in the case where a data signal having large jitter is compared with a clock signal, and a phase-locked state detecting circuit using the same.
The present invention provides, in short, a frequency comparator for comparing a clock frequency with a frequency of a data signal by using first to fourth clock signals having an equal clock frequency and of which respective phases of reference edges are at 0°, 90°, 180° and 270°, includes: first and second detectors; and a phase change detector.
The first detector receives the data signal synchronously with the first and third clock signals and detects whether or not a phase of a signal transition point of the data signal lies with respect to the clock signal in a range from 0° to 180°. The second detector receives the data signal synchronously with the second and fourth clock signals and detects whether or not a phase of the signal transition point lies with respect to the clock signal in a range from 90° to 270°. The phase change detector receives outputs of the first and second detectors, detects a change in the phase of the signal transition point with respect to the clock signal, and outputs a result of comparison between the clock frequency and the frequency of the data signal.
According to another aspect of the invention, there is provided a phase-locked state detecting circuit for detecting a phase-locked state of a clock and a data signal and outputting a phase-locked state detection signal, includes; a frequency comparator; a counting processing unit; and a hysteresis generating unit.
The frequency comparator compares a clock frequency with a frequency of the data signal, and activates a control signal when the frequencies are different from each other. The counting processing unit counts an activate period of the control signal per predetermined period on the basis of the clock, and outputs an overflow detection signal when a count value exceeds a predetermined number. The hysteresis generating unit makes the phase-locked state detection signal inactive when the overflow detection signal is activated a predetermined number of times consecutively after the phase-locked state detecti
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nu Ton My-Trang
LandOfFree
Frequency comparator with malfunction reduced and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Frequency comparator with malfunction reduced and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Frequency comparator with malfunction reduced and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3245163