Semiconductor device having triple well structure

Details Semiconductor device having triple well structure Semiconductor device having triple well structure

2001-04-05

2004-04-27

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

With pn junction isolation

C257S371000

Reexamination Certificate

active

06727573

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a method for fabricating the same, more specifically to a semiconductor device having a triple well structure and a method for fabricating the same.
Recently, it is required in various semiconductor devices, such as DRAMs, non-volatile memories, etc. that specific voltages are applied to a plurality of wells, and the so-called triple well structure in which in addition to usual N-well and P-well, a third well having a well formed in a P-well or an N-well and having a conductivity type different from that of the P-well or the N-well is noted. A method for forming the triple well structure by high-energy ion implantation is especially advantageous in terms of throughput and is expected to be developed.
A conventional method of fabricating a semiconductor device for forming the triple well structure by high-energy ion implantation will be explained with reference to
FIGS. 14A-14C
,
15
A-
15
C and
16
A-
16
C.
FIGS. 14A-14C
,
15
A-
15
C and
16
A-
16
C are sectional views of the semiconductor device in the steps of the conventional method for fabricating a semiconductor device, which explain the method.
In this explanation, a DRAM having a usual CMOS wells, a P-well for a peripheral circuit, which is formed in an N-well and having a voltage different from that of the CMOS P-well, and a P-well for a memory cell, which is formed in an N-well will be exemplified.
First, a field oxide film
102
is formed on a P-type silicon substrate
100
by, e.g., the usual LOCOS (LOCal Oxidation of Silicon) method. In
FIG. 14A
, a device region defined by the field oxide film
102
corresponds to, from the left in the drawing, a PMOS region
104
for a peripheral circuit, an NMOS region
106
for a peripheral circuit, an NMOS region
108
for a peripheral circuit formed in a different-voltage well and a memory cell region
110
.
Then, the silicon substrate is thermally oxidized by dry oxidation at, e.g., 900° C. to form an about 10 nm-thick silicon oxide film
112
in the device region (FIG.
14
A).
Subsequently, a photoresist
114
exposing the PMOS region
104
, the NMOS region
108
and the memory cell region
110
is formed by the usual lithography.
Then, phosphorus ions are implanted with the photoresist
114
as a mask to form N-type diffused layers
116
,
118
in regions inside the silicon substrate
100
(FIG.
14
B). The phosphorus ions are implanted at, e.g., 1 MeV acceleration energy and a 3×10
13
cm
−2
dose.
The N-type diffused layers
116
,
118
are for forming parts having higher concentrations in the bottoms of the wells. Conditions for the ion implantation are restricted by punch-through resistance between the P-well in the N-well and the silicon substrate
100
and the latch-up resistance.
Then, the photoresist
114
is removed, and then a photoresist
120
exposing the PMOS region
104
and the NMOS region
108
is formed by the usual lithography.
Subsequently, with the photoresist
120
as a mask phosphorus ions are implanted to form N-wells
122
,
124
connected to the N-type diffused layers
116
,
118
(FIG.
14
C).
This ion implantation is performed, e.g., at 200 keV acceleration energy and a 4×10
12
cm
−2
dose, and 80 keV acceleration energy and a 1×10
12
cm
−2
dose. The higher energy implantation corresponds to channel stop ion implantation for maintaining a threshold voltage of a field transistor sufficiently high, and the lower energy implantation corresponds to ion implantation for threshold voltage control of a PMOS transistor in the PMOS region
104
.
The thus formed N-well
124
finally functions to electrically isolate the different-voltage P-well from the silicon substrate
100
and is formed in an annular region surrounding the memory cell region
110
.
Next, the photoresist
120
is removed, and then a photoresist
128
exposing the NMOS region
106
and a region
126
inside the NMOS region
108
, where the P-well is to be formed. The region
126
for the P-well to be formed in is arranged to position inside the inner edge of the N-well
124
, and the outer edge of the N-well
124
is covered with the photoresist
128
.
Subsequently, boron ions are implanted with the photoresist
128
as a mask to form a P-well
130
in the silicon substrate
100
in the NMOS region
106
and a P-well
132
in the silicon substrate
100
in the region
126
for the P-well to be formed in (FIG.
15
A). The P-well
132
is electrically isolated from the silicon substrate
100
by the N-type diffused layer
118
positioned below the P-well
132
, and accordingly is formed to be shallower than the N-type diffused layer
118
.
The ion implantation for forming the P-wells
130
,
132
are performed three times by implanting boron ions, e.g., at a 180 keV acceleration energy and a 1.5×10
13
cm
−2
does in the first implantation, at a 100 keV acceleration energy and a 4×10
12
cm
−2
dose in the second implantation, and at a 50 keV acceleration energy and a 1×10
12
cm
−2
dose in the third implantation.
The ion implantation at the high energy (180 keV) is for forming a heavily-doped part at the bottom of the P-wells
130
,
132
and is determined by punch-through resistance and latch-up resistance between the n-type source/drain of the NMOS formed in the NMOS region
108
, and the N-type diffused layer
118
.
The ion implantation at the middle energy (100 keV) is for channel stop for maintaining a threshold voltage of the field transistor sufficiently high.
The ion implantation at the low energy (50 keV) is for controlling threshold voltages of the NMOS in the NMOS regions
106
,
108
.
Then, the photoresist
128
is removed to perform in the entire surface of the silicon substrate
100
ion implantation of, boron ions at, e.g., 18 keV acceleration energy and a 2×10
12
cm
−2
dose, whereby the PMOS formed in the N-well
122
and the NMOS formed in the P-wells
130
,
132
can have threshold voltages of required values.
Then, a photoresist
134
exposing the memory cell region
110
is formed by the usual lithography techniques.
Subsequently, boron ions are implanted with the photoresist
134
as a mask to form the P-well
136
in the side of the memory cell region
110
opposed to the surface of the silicon substrate
100
(FIG.
15
B).
Boron ions are implanted four times at, e.g., 180 keV acceleration energy and a 5×10
12
cm
−2
dose in the first ion implantation, 100 kev acceleration energy and a 2×10
12
cm
−2
in the second ion implantation, 50 keV acceleration energy and a 1×10
12
cm
−2
dose in the third ion implantation, and 18 keV acceleration energy and a 5×10
12
cm
−2
dose in the fourth ion implantation.
The ion implantation at the high energy (180 keV) is for forming a heavily doped part at the bottom of the P-well
136
and is determined by punch-through resistance and latch-up resistance between the source/drain of the NMOS formed in the memory cell region
110
and the N-type diffused layer
118
.
The ion implantation at the middle energy (100 keV) is for maintaining a threshold voltage of the field transistor sufficiently high.
The ion implantation at the low energy (50 keV and 18 keV) is for controlling threshold voltages of the NMOS in the memory cell regions
110
.
As described above, the conventional semiconductor fabrication method needs four lithography steps to form the triple-well structure including the N-wells
122
,
124
, the P-well
130
and the different-voltage P-wells
132
,
136
(FIG.
15
C).
The photoresist
128
a
shown in
FIG. 16A
is used in the step of
FIG. 15A
to concurrently form the P-wells
120
,
132
,
136
. However, in this case it is necessary to separately conduct the step of the ion implantation for the NMOS in the memory cell region
110
having an adjusted threshold voltage, and to this end, the step of forming the photoresist
134
a
exposing the memory cell region
110
is needed (FIG.
16
B). C

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