Vertical MISFET transistor surrounded by a Schottky barrier...

Details Vertical MISFET transistor surrounded by a Schottky barrier... Vertical MISFET transistor surrounded by a Schottky barrier...

2002-06-10

2004-03-16

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Schottky barrier

With means to prevent edge breakdown

C257S486000, C257S483000, C257S127000, C257S130000, C257S589000, C257S605000, C257S328000, C438S138000, C438S268000, C438S270000, C438S570000

Reexamination Certificate

active

06707128

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-179014, filed Jun. 13, 2001, the entire contents of which are incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device which includes MISFET (insulated gate field effect transistor) and Schottky barrier diode (SBD) on a single semiconductor chip, and which is for use in, for example, a synchronization rectifier circuit.
2. Description of the Prior Art
As a power semiconductor device, a MISFET with a vertical structure for flowing a large current in a vertical direction of the semiconductor substrate, an IGBT driven by a MIS gate, etc have been utilized. As the gate structure of the power MISFET used when a breakdown voltage of, for example, about 30-40 V is needed, a planar structure and trench structure are widely known. In the planar structure, a flat gate electrode is used. In the trench structure, a gate electrode is buried in a trench to employ the sidewall of the trench as a channel region, in order to achieve a fine and low-loss structure.
The power MISFET with the trench structure has a number of juxtaposed MISFET cells in the semiconductor substrate. This structure is considered more advantageous than the power MISFET of the planar structure in that the performance can be enhanced (the loss can be reduced) simply by reducing the channel resistance.
The MISFET can be used as a step-down synchronization rectifier DC—DC converter circuit that is for use in, for example, a portable electronic device for efficiently converting a high DC input voltage into a low DC output voltage.
FIG. 8
shows an example of a connection relationship between the synchronization rectifier circuit and the load circuit.
In this case, an NMISFET as an “H” side transistor Q
1
is connected between a DC power supply (not shown) and output terminal OUT, a Schottky barrier diode (SBD)
80
is reversely connected between the output terminal OUT and a ground potential GND, and an NMISFET as an “L” side transistor Q
2
for switching is connected in parallel with the SBD
80
. Each of the parasitic PN-junction diodes D
1
and D
2
is provided between the source/drain of a corresponding one of the transistors Q
1
and Q
2
. Further, an inductor such as a coil L, serving as a load circuit, and a smoothing capacitor C are connected in series between the output terminal OUT and ground potential GND.
As well known, in the synchronization rectifier circuit shown in
FIG. 8
, the “H” side transistor Q
1
is intermittently and cyclically driven by a pulse signal having a duty ratio controlled in accordance with a desired output voltage, thereby providing the desired output voltage to the smoothing capacitor C.
While the “H” side transistor Q
1
for load driving is in the ON state, a driving current is supplied from the DC power supply to the load circuit (coil L) via the “H” side transistor Q
1
, thereby accumulating energy in the coil L. During the time from when the “H” side transistor Q
1
has been turned off, to when “L” side transistor Q
2
has been turned on, the energy accumulated in the coil L (counterelectromotive force) is discharged from the ground potential GND via the parasitic PN diode D
2
of the “L” side transistor Q
2
and the SBD
80
. This parallel connection of the transistor Q
2
and SBD
80
reduces the power loss.
If the “L” side transistor Q
2
and SBD
80
are formed on different chips and assembled in different packages, the degree of freedom of design is limited in cost, mount area (occupied space), etc.
Further, if the “L” side transistor Q
2
and SBD
80
are formed on different chips, and are mounted on a single lead frame in an electrically separated condition, it is necessary to connect, using an external wire, between the source of the transistor Q
2
and the anode of the SBD
80
, and also between the drain of the transistor Q
2
and the cathode of the SBD
80
(for example, to connect them to the lead frame by wire bonding), thereby increasing the resistance or inductance component of the entire circuit.
For eliminating the necessity of connecting the transistor Q
2
and SBD
80
by the external wire to reduce the cost, the mount area and the resistance or inductance component of the wiring layer, an NMISFET/SBD-mounted semiconductor device has been proposed, in which the transistor Q
2
and SBD
80
are provided on a single semiconductor chip, and the source and drain electrodes of the transistor Q
2
are made to also serve as the anode and cathode of the SBD
80
, respectively.
FIG. 9
illustrates perspectively an example of a pattern layout on a chip employed in the conventional NMISFET/SBD-mounted semiconductor device.
On a semiconductor chip
40
, an SBD is provided in an SBD-forming region
44
(indicated by the broken line in
FIG. 9
) that is a part of the FET-forming region for forming an NMISFET. On the top surface of the chip, a first common main electrode
41
, which serves as both the source electrode of the NMISFET and the anode of the SBD, is provided, and the surface gate electrode
42
of the NMISFET is provided, isolated from the first main electrode
41
by an insulation film
43
. On the reverse surface of the chip, a second common main electrode (see FIG.
10
), which serves as both the drain electrode of the NMISFET and the cathode of the SBD, is provided.
FIG. 10
is a schematic sectional view taken along line X—X of FIG.
9
.
Specifically, it shows several NMISFET cells of the trench gate structure and an SBD provided on an N
+
/N
−
substrate that is obtained by growing an epitaxial N
−
layer on an N
+
semiconductor substrate.
In
FIG. 10
, reference numeral
50
denotes a semiconductor substrate, reference numeral
51
an N
−
layer (epitaxial layer), reference numeral
52
a P base layer formed in the N
−
layer in the FET-forming region, and reference numeral
53
N
+
source regions in the P base layer. Further, gate trenches extend from the surfaces of the N
+
source regions
53
to the N
−
layer
51
.
Reference numeral
55
denotes a gate insulation film provided on the inner wall of each gate trench, and reference numeral
56
a trench gate electrode made of doped polysilicon and buried in each trench gate. Polysilicon wiring layer (not shown) extends from each trench gate electrode to a position away from the gate trench array.
Reference numeral
57
denotes a guard ring region formed in the N
−
layer along the entire (or part of the) peripheral portion of the chip, and an island-shaped SBD-forming region
58
is provided between the guard ring region
57
and FET-forming region
54
.
Reference numeral
59
denotes an interlayer insulation film provided on the substrate in the FET-forming region, and contact holes are formed in predetermined portions of the film. Reference numeral
61
denotes an oxide film provided on the portion of the substrate that includes part of the guard ring region
57
.
A barrier metal
62
is continuously provided over part of the guard ring region
57
, the N− layer
51
in the SBD-forming region
58
, part of each N
+
source region
53
, and part of the P base layer
52
.
The aforementioned first main electrode
41
made of a metal (such as aluminum), which serves as both the SBD anode and FET source electrode, is provided on the barrier metal
62
. Further, the surface gate electrode
42
(see
FIG. 9
) is provided on the polysilicon gate wiring layer (not shown) in the FET-forming region
54
, and is isolated from the first main electrode
41
by the interlayer insulation film
43
(FIG.
9
).
Furthermore, on the reverse surface of the chip, the aforementioned second common main electrode
45
, which serves as both the FET drain electrode and SBD cathode, is provided.
In the above-described NMISFET/SBD-mounted semiconductor device, the drain current flowing

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