Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Solder wettable contact – lead – or bond
Reexamination Certificate
2001-06-05
2004-05-04
Chambliss, Alonzo (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Solder wettable contact, lead, or bond
C257S780000, C257S783000, C257S784000, C257S786000, C257S787000, C174S050510, C174S050510, C361S772000, C361S777000, C361S808000
Reexamination Certificate
active
06731013
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a semiconductor device which is miniaturized to almost chip size to be suitable particularly for density packaging, and relates to a wiring substrate (printed circuit board) therefor, and to a package stack semiconductor device having a plurality of such a semiconductor device.
BACKGROUND OF THE INVENTION
Recently QFP (Quad Flat Package) type, BGA (Ball Grid Array) type, and CSP (Chip Size package) type semiconductor devices have been widely used as what meets the needs of miniaturizing electronic equipment.
These semiconductor devices need more and more external connection terminals since signal processing of a semiconductor chip (semiconductor-element) mounted therein has been highly speeded and highly facilitated. In such case, the BGA type whose external connection terminals are provided on a bottom face of a semiconductor device in a two-dimensional manner is widely adopted.
Of these BGA type semiconductor devices, conventionally known is a semiconductor device whose semiconductor chip and wiring substrate are connected to each other by wire bonding with a circuit forming surface of the semiconductor chip facing upward, wherein the semiconductor chip is conducted to external connection terminals through the wiring pattern of the wiring substrate. “Upward” means that the circuit forming surface is on the other side of the surface of semiconductor chip facing the wiring substrate.
Such a conventional resin-sealed semiconductor device is disclosed in Japanese Unexamined Patent Publication No. 121002/1997 (Tokukaihei 9-121002) (published date: May 6, 1997).
A semiconductor device which has a structure like this, as shown in
FIG. 20
, has a wiring substrate
67
, a semiconductor chip
52
which is mounted on the wiring substrate
67
, an Au wire
53
which connects the semiconductor chip
52
to a terminal section
55
of the wiring substrate
67
, a resin sealing section
61
which seals the semiconductor chip
52
and the Au wire
53
with resin by transfer molding.
The wiring substrate
67
has an insulating substrate
63
, an insulating material
62
as an insulating layer on the chip side, and a wiring pattern provided between the insulating substrate
63
and the insulating material
62
. That is, the wiring substrate
67
has a metallic wiring pattern which is formed on the insulating substrate
63
provided with a through hole
58
, and the insulating material
62
is bonded with the metallic wiring pattern thereon.
Further, the wiring substrate
67
is provided with the through hole
58
through the insulating substrate
63
in a direction of thickness according to the wiring pattern. Thus, the wiring pattern is partially exposed on the through hole
58
, and the exposed portion of the wiring pattern makes up a land section
56
in FIG.
20
.
In addition, the wiring substrate
67
includes an external connection terminal
60
which is formed as a solder ball by reflow soldering. Thus, through the through hole
58
, the external connection terminal
60
is connected to the land section
56
provided on the upper side of the through hole
58
, and hangs down like a ball from the lower side of the through hole
58
.
Among such semiconductor devices, there has been known a semiconductor device having a plurality of semiconductor chips mounted therein in order to increase added values and capacity of a memory and the like in portable devices. For example, a multi-chip module which is provided with a plurality of board-shaped semiconductor chips side by side (in a direction of surface) is known.
However, since semiconductor chips are provided side by side, it is impossible to make a semiconductor device whose area (the area of bottom surface) is smaller than the total area of these semiconductor chips.
In view of this drawback, there has been proposed a semiconductor device (hereinbelow, referred to as stacked package) which improves packaging density by stacking a plurality of semiconductor chips in a direction of thickness and putting these chips in a semiconductor device.
An example of such a stacked package is disclosed in Japanese Unexamined Patent Publication No. 204720/1999 (Tokukaihei 11-204720) (published date: Jul. 30, 1999). The stacked package mentioned above, as shown in
FIG. 21
, has semiconductor chips
52
a
and
52
b
which are stacked together to be mounted on the wiring substrate
67
which insulates electricity. Further, an external connection terminal
60
is provided in a matrix pattern on a land section
56
in the stacked package so that the external connection terminal
60
hangs down from the lower surface of the wiring substrate
67
. Thus, the stacked package has the CSP structure which has almost the same size as the semiconductor chip
52
a
and
52
b.
The method of fabricating the stacked package like this is as follows. In the first place, the first semiconductor chip
52
b
is die-bonded on the wiring substrate
67
with its circuit forming surface facing upward, and then the second semiconductor chip
52
a
is die-bonded thereon.
Thereafter, each semiconductor chip
52
a
,
52
b
is connected to the terminal section
55
of the wiring substrate
67
with an Au wire
53
by wire bonding. In addition, each semiconductor chip
52
a
,
52
b
, and the Au wire
53
are sealed with a resin sealing section
61
by transfer molding. Then, a solder ball is provided as the external connection terminal
60
on the land
56
by reflow soldering. The ball is used as the external connection terminal
60
. The stacked package mentioned above is produced this way.
Depending on the type of the semiconductor chips
52
a
and
52
b
and the position where the external connection terminals
60
are drawn, it is sometimes impossible to form wiring patterns freely on the wiring substrate
67
which has a single layer wiring pattern like the semiconductor device mentioned above. Thus, as shown in
FIG. 22
, a multi-layer wiring substrate
68
whose wiring pattern, made of Cu, is provided on its both surfaces is sometimes used.
The wiring pattern of the multi-layer wiring substrate is provided not only on the surface of the insulating substrate
63
, which is a base material, where the semiconductor chip is mounted (hereinbelow referred to as side A), but also on the surface where the external connection terminal
60
is formed (hereinbelow referred to as side B). The wiring pattern of side B is usually protected with a solder resist
57
.
Further, conduction is ensured between the land section
56
of the wiring pattern on side A and the land section
56
of the wiring pattern on side B which faces side A through the through hole
58
, by filling the through hole
58
with a conductor
59
such as a conductive paste.
However, there is a problem. As shown in
FIG. 23
, in the foregoing conventional wiring substrate
68
which is provided with the wiring patterns on side A and side B, inadequate wire bonding is incurred between the semiconductor chip
52
and the terminal section
55
.
That is, when the semiconductor chip
52
and the terminal section
55
are connected by wire bonding, the load applied on the terminal section
55
in a direction of thickness of the insulating substrate
63
to make connection causes deformation of the insulating substrate
63
. As a result, a load cannot be applied sufficiently on the terminal section
55
, and consequently, inadequate wire bonding tends to occur, which, in turn, may cause electrical connection failure between the semiconductor chip
52
and the terminal section
55
.
Meanwhile, as shown in
FIG. 20
, the wiring substrate
67
which is provided with a wiring pattern only on one surface can avoid wire bonding problem mentioned above. That is, side B of the wiring substrate
67
does not have any wiring pattern, or any solder resist to protect wiring patterns, and thus the surface of side B is flat.
Therefore, since the wiring substrate
67
provided with the wiring pattern only on one surface has side B which is flat, the load applied on the terminal section
55
Fukui Yasuki
Ishihara Seiji
Juso Hiroyuki
Yano Yuji
Chambliss Alonzo
Nixon & Vanderhye
Sharp Kabushiki Kaisha
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