Plating method, interconnection forming method, and...

Details Plating method, interconnection forming method, and... Plating method, interconnection forming method, and...

2001-06-19

2004-03-23

Valentine, Donald R. (Department: 1742)

Chemistry: electrical and wave energy

Apparatus

Electrolytic

C204S198000, C204S241000, C204S242000, C204S274000, C204S275100, C118S423000

Reexamination Certificate

active

06709555

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a nonaqueous plating method for use in forming a liner for plating before an electrically conductive metal such as copper or the like is embedded by plating in a conductor-embedding fine recess that is defined in a surface of a semiconductor substrate, an interconnection forming method for use in forming an interconnection using such a liner, and apparatus for carrying out such methods.
BACKGROUND OF ART
Generally known plating processes include electroless and electrolytic plating processes which are carried out in an aqueous solution. However, some base materials to be plated are susceptible to water, and those base materials which have a hydrophobic surface or which are not electrically conductive are difficult or impossible to plate.
In view of the above difficulties, there have been developed and put to practical use various nonaqueous plating methods which do not use an aqueous solution. They include an evaporation plating process as a vacuum technology, a vapor-phase plating process based on sputtering or the like, a hot-dip plating process for dipping a workpiece in a molten metal, a thermal spraying process for applying a molten metal to a workpiece, a baking process based on the thermal decomposition of an organic metal, and a process using a mercury amalgam.
Aluminum or aluminum alloy has generally been used as a metal material for forming interconnection circuits on semiconductor substrates. In recent years, however, there has been a noticeable tendency to use copper as such a metal material. The reasons for using copper as an interconnection material are that copper is advantageous about a signal delay phenomenon as its electric resistivity is 1.72 &mgr;&OHgr;cm that is nearly 40% lower than the electric resistivity of aluminum, the electromigration resistance of copper is much higher than that of presently used aluminum, and it is easier to employ the dual damascene process on copper than on aluminum, resulting in a higher possibility to manufacture complex, fine multilayer interconnection structures relatively inexpensively.
There are available three processes for embedding a metal such as copper simultaneously in interconnection trenches and via holes according to the dual damascene principle, i.e., {circle around (1)} CVD, {circle around (2)} sputter reflow, and {circle around (3)} plating. Of these processes, the plating process allows the metal to be embedded in fine recesses with good embeddability and has a strong tendency to form lines of good conductivity according to a relatively easy, inexpensive process. Therefore, it is becoming the common practice to incorporate the plating process in a semiconductor mass-production line to produce interconnections according to a design rule of at least 0.18 &mgr;m.
FIGS. 17A through 17C
of the accompanying drawings show a basic process of plating a surface of a semiconductor substrate with copper to fabricate a semiconductor device with a copper interconnection. As shown in
FIG. 17A
, a semiconductor substrate W includes a semiconductor base
1
with a semiconductor device formed thereon, an electrically conductive layer
1
a
disposed on the semiconductor base
1
, an insulating film
2
of SiO
2
deposited on the electrically conductive layer
1
a
and having a fine recess
5
which comprises a contact hole
3
and an interconnection trench
4
defined therein by lithography and etching, and a barrier layer
6
of TaN or the like deposited on the surface formed so far.
As shown in
FIG. 17B
, the surface of the semiconductor substrate W is plated with copper to fill copper
7
in the recess
5
in the semiconductor base
1
and deposit copper
7
on the barrier layer
6
. Thereafter, the assembly is chemically and mechanically polished (CMP) to remove the copper
7
on the barrier layer
6
and also the barrier layer
6
until the surface of the copper
7
filled in the contact hole
3
and the interconnection trench
4
lies substantially flush with the surface of the insulating film
2
. In this manner, an embedded interconnection of the copper
7
is formed as shown in FIG.
17
C.
For embedding the copper
7
in the recess
5
defined in the surface of the semiconductor base
1
according to the electrolytic plating process, for example, it is widely practiced to form a liner (undercoat film)
8
, which will serve as a seed layer, on the surface of the barrier layer
6
on the semiconductor substrate W before the copper is plated, as shown in FIG.
18
A. The liner (seed layer)
8
is deposited for the primary purpose of supplying a sufficient electric current to reduce metal ions in the electrolytic liquid using the surface of the seed layer as an electric cathode, so that the reduced metal ions are precipitated as a metal solid. When the electroless plating process is employed, then it is the wide practice to deposit a catalytic layer in place of a seed layer, as the liner
8
.
Presently, the conventional nonaqueous plating methods find limited applications, however, because they need special vacuum equipment, require base materials for plating to be heat-resistant, and are difficult to produce accurate plated films.
Generally, the liner
8
is often formed by sputtering. However, the growth of the liner
8
by sputtering makes it difficult to form the liner
8
that covers the entire surface of the recess
5
as the recess
5
becomes narrower and deeper. For example, if the width W
1
of the opening of the recess
5
is 0.25 &mgr;m, then it is thought that the limit depth D of the recess
5
for forming a sound liner
8
on the entire surface of the recess
5
according to sputtering film growth is about 1.25 &mgr;m.
If the depth of the recess
5
exceeds the limit depth D, then, as shown in
FIG. 18A
, only an incomplete film is formed on the side walls of the fine recess
5
defined in the surface of the substrate W. Furthermore, when the surface which faces the plasma, while the sputtering process is being carried out, is heated to the limit temperature, sputtering copper molecules are coagulated into precipitated granules
9
, which inhibit the formation of a continuous film.
If an attempt is made to embed a metal according to electrolytic plating on the incomplete liner, then the plated metal grows in equal directions at equal rates from sound electrically conductive surfaces of the liner
8
, but is restrained or prevented from growing from defective regions of the liner
8
. As a result, a void
10
is produced in the copper
7
that is finally embedded in the recess
5
, as shown in
FIG. 18B
, or a large cavity (plating failure)
11
is produced in the copper
7
that is finally embedded in the recess
5
, as shown in FIG.
18
C.
If the thickness of the liner
8
is increased to a value much greater than the normal thickness to greatly increase the area covered by the liner
8
in order to avoid the above drawbacks, as shown in
FIG. 19A
, then overhanging regions
12
project to a large extent from shoulders of the opening of the recess
5
. When the assembly is plated, the path extending across the entrance of the recess
5
is quickly reduced and closed as the plating process is in progress. As a consequence, copper ions supplied into the recess
5
become unavailable in the plating process, leaving the plating liquid. Therefore, as shown in
FIG. 19B
, a seam
13
often occurs as a thin slit-like defect in the copper
7
embedded in the recess
5
.
The void
10
, the cavity
11
, and the seam
13
, which are plating defects, are extremely harmful to the electrically conductive path. It is thus desirable to eliminate those defects and produce a continuous integral electrically conductive path for achieving a sufficient current capacity, suppressing a signal delay, and improving the electromigration resistance. This also holds true for the electroless plating process which uses a catalytic layer as the liner in place of a seed layer in the electrolytic plating process.
DISCLOSURE OF INVENTION
The present invention has been made in view of the ab

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