Light emitting semiconductor device

Details Light emitting semiconductor device Light emitting semiconductor device

2002-12-19

2004-07-13

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Incoherent light emitter structure

With heterojunction

C257S079000, C257S088000, C257S101000, C372S045013, C372S046012

Reexamination Certificate

active

06762437

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a light emitting semiconductor device, such as a light emitting diode array (hereinafter referred to as “LED array”), used as a light source for an electrophotographic printer.
2. Description of the Related Art
A conventional LED array to realize a high light emitting efficiency is discloses, for example, in U.S. Pat. No. 6,222,208. The LED array comprises an active layer (made of n-type Al
y
Ga
1−y
As), an upper cladding layer (made of n-type Al
z
Ga
1−z
As) formed on the active layer, a p-type semiconductor region selectively formed in the upper clad and active layers by diffusing zinc (Zn), and a patterned layer. The patterned layer is defined as an LED surface layer formed on the upper cladding layer and includes a contact semiconductor layer, a dielectric interlayer (or dielectric layers), and an electrode layer (or electrode layers). The contact semiconductor, dielectric, and electrode layers in the patterned layer are partly etched by a photolithography/etching process to make desired patterns.
High light-output efficiency is realized in the LED array for the following reasons. Minority carriers (electrons and holes) are injected into the active layer through a pn-junction interface. Electrons injected into the p-type active layer (Zn-diffused region in the active layer) cannot diffuse out into the p-type upper cladding layer due to the energy barrier formed at the interface between the p-type upper cladding layer (Zn-diffused region in the upper cladding layer) and the p-type active layer. Holes injected into the n-type active layer cannot diffuse out into the n-type lower cladding layer due to the energy barrier formed at the interface between the n-type active layer and the n-type lower cladding layer.
In order to well confine the injected carriers inside the active layer and obtain extremely high light-output efficiency, it is required that an energy band gap of the upper cladding layer is sufficiently large compared to that of the active layer. A large difference in energy band gaps between the active layer and the cladding layer serves high-enough energy barrier for the injected carrier confinement at the interface between the p-type layer and the p-type cladding layer. Therefore, the upper cladding layer is required to have much higher aluminum (Al) content than that of the active layer. That is, a value of z in Al
z
Ga
1−z
As is required to be much larger than that of y in Al
y
Ga
1−y
As.
However, when the content of Al in the upper cladding layer is large (for example, z=0.6), the surface of the upper cladding layer is prone to be etched by an etchant that is used to etch a pn-junction regions formed in the contact layer. The etchant is, for example, a solution consisting of phosphoric acid, hydrogen peroxide, and diluted water. Accordingly, a gap space my be formed in the upper cladding layer by eroding the interface region between the contact layer and the upper cladding layer when the Al content is high in the upper cladding layer and the pn-unction regions formed in the contact layer are etched by wet-etching.
FIG. 14
shows an LED array having gap spaces
321
-
324
as caused by etchant erosion at the interface between the contact layer and the cladding layer. Reference number
301
denotes a semiconductor substrate,
302
a semiconductor epitaxial layer,
303
a buffer layer,
304
an n-type lower cladding layer,
305
an n-type active layer,
306
an n-type upper cladding layer,
307
an n-type contact layer,
308
a p-type diffusion region,
309
an dielectric interlayer,
310
a p-type contact layer,
311
a p-side electrode (a discrete electrode), and
312
an n-side electrode (a common electrode).
FIGS. 15 and 16
show A
1
and A
2
sections in
FIG. 14
, respectively (the discrete electrode
311
is not explicitly drawn in FIGS.
15
and
16
). When the gap space
321
or
324
formed at the interface between the upper cladding layer and the contact layer provides a large step or cave-shaped portion near the edge region of an n-type contact layer windows
307
b
formed by wet-etching the pn-junction regions in the contact layers
307
and
310
. Consequently, the dielectric interlayer film and discrete electrode film cannot cover over the step at the n-type contact layer window region. This results in an insulation defect in the dielectric interlayer
309
(
FIG. 15
) or a disconnection detect in the electrode
311
(FIG.
16
).
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a light emitting semiconductor device and its manufacturing method, where one can increase the light emitting efficiency and reduce the defective ratio in the formation of the patterned layer.
In order to achieve the object, a light emitting semiconductor device according to the invention comprises an active layer made of a first conductive type semiconductor epitaxial layer provided on a substrate, an upper cladding layer made of the first conductive type semiconductor epitaxial layer and provided on the active layer, wherein the upper cladding layer comprises a stack of upper cladding sub-layers including a first upper cladding sub-layer to a M-th cladding sub-layer provided on the active layer in this order, whereas said M is an integer not less than 2. The first upper cladding sub-layer has an energy band gap larger than that of the M-th upper cladding sub-layer and each of energy band gaps of the upper cladding sub-layers is larger that of the active layer. The light emitting semiconductor device further comprises a selective diffusion region and a patterned layer. In the selective diffusion region, the second conductive type impurity is diffused through a diffusion window, or an opening window, formed in a diffusion barrier film, or dielectric layer, with the diffusion front reaching to the active layer. The selective diffusion region is formed in the contact, upper cladding, and active layers. The patterned layer is provided on the upper cladding layer or the diffused region, or on both the upper cladding layer and the diffused region, and has an etched region at the pn-junction area in the contact layer such that at least a part of the upper cladding layer or at least a part of the diffused region is exposed.


REFERENCES:
patent: 5189496 (1993-02-01), Kuwabara
patent: 5889805 (1999-03-01), Botez et al.
patent: 6011811 (2000-01-01), Ohlander et al.
patent: 6133588 (2000-10-01), Ogihara et al.
patent: 6180961 (2001-01-01), Ogihara et al.
patent: 6222208 (2001-04-01), Ogihara et al.

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