Wave transmission lines and networks – Coupling networks – Electromechanical filter
Reexamination Certificate
2002-07-25
2004-09-21
Summons, Barbara (Department: 2817)
Wave transmission lines and networks
Coupling networks
Electromechanical filter
C333S191000, C333S192000, C438S051000, C257S684000, C257S704000
Reexamination Certificate
active
06794958
ABSTRACT:
BACKGROUND
The present invention relates to semiconductor circuit fabrication technology, and more particularly, to connection and protection of various circuit elements using a cap.
Semiconductor circuits and devices are typically manufactured by depositing and patterning one layer at a time. Beginning at a bottom layer, each layer is deposited and then patterned using an etching technique before any subsequent layers are deposited. A popular etching technique includes a number of steps. First, the entire layer is covered using photoresist material. Next, portions of the photoresist material are exposed to radiation (such as ultraviolet light) in a desired pattern. Then, the exposed portions of the photoresist are removed and portions of the layer under the removed portions of the photoresist are also removed. Remaining portions of the layer form the desired pattern and has the non-exposed portions of the photoresist covering the remaining portions of the layer. Finally, the photoresist over the remaining portions of the layer is removed. This process allows the patterning of each layer such that any one layer can overlap any and all other layers fabricated before, or under, that one layer.
For example,
FIGS. 1A and 1B
illustrate a device
110
having two resonators
120
(first resonator) and
130
(second resonator) fabricated over a substrate
112
.
FIG. 1A
is a top view of the device
110
and
FIG. 1B
is a cutaway cross-sectional side view of the device
110
, cut along line A—A of FIG.
1
A.
Here, bottom electrode layers
122
and
132
were fabricated by first depositing a single bottom electrode layer covering the entire substrate
112
and then patterning that single bottom electrode layer using an etching technique. Above the bottom electrodes
122
and
132
, a crystalline layer
114
is fabricated using a similar deposit-and-etch technique. Above the crystalline layer
114
, a top electrode layer
116
is fabricated again using a similar deposit-and-etch technique.
However, for some purposes, the application of the deposit-and-etch technique may have undesirable consequences. For example, in thin film bulk acoustic resonator (FBAR) manufacturing processes, quality of the crystalline layer
114
may vary widely depending on residual photoresist remaining from the etching process of the previous layer. Further, the crystalline layer
114
may develop gaps or cracks when fabricated over an edge, for example edge
115
, of its underlying layer. Such cracks or gaps lead to susceptibility to electrostatic discharges.
Accordingly, there remains a need for a technique of fabricating semiconductor devices that overcomes these problems and an apparatus embodying the method.
SUMMARY
The need is met by the present invention. According to a first aspect of the present invention, a method of fabricating an apparatus is disclosed. First, a device chip is fabricated, the device chip including circuit elements fabricated on a substrate and also including a first contact point and a second contact point. Next, a cap is fabricated including a connector. Finally, the cap is placed on the device chip where the connector makes contact with the first contact point and the second contact point.
According to a second aspect of the present invention, an apparatus includes a device chip including circuit elements fabricated on a substrate and a cap. The device chip has a first contact point and a second contact point. The cap covers at least a portion of the device chip. Further, the cap has a connector for connecting the first contact point and the second contact point of the device chip.
According to a third aspect of the present invention, an apparatus includes a device chip and a cap. The device chip includes a substrate and circuit elements fabricated on the substrate. The device chip also includes a first resonator and a second resonator, each resonator having its own bottom electrode, piezoelectric material, and top electrode, each top electrode connected to a landing pad. The cap has a connector connecting landing pad of the first resonator to landing pad of the second resonator.
REFERENCES:
patent: 4736128 (1988-04-01), Takoshima et al.
patent: 5608362 (1997-03-01), Nishimura et al.
patent: 5920242 (1999-07-01), Oya et al.
patent: 5939956 (1999-08-01), Arimura et al.
patent: 6157076 (2000-12-01), Azotea et al.
patent: 8-191230 (1996-07-01), None
patent: 11-274886 (1999-10-01), None
Philliber Joel Alan
Ruby Richard C.
Agilent Technologie,s Inc.
Summons Barbara
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