Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2002-12-09
2004-03-23
Nguyen, Long (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S333000, C327S332000, C327S323000
Reexamination Certificate
active
06710632
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to a drive circuit that controls drive current supplied to a load by using a clamp circuit.
BACKGROUND OF THE INVENTION
In drive circuits that supply drive current for converting electrical energy into thermal energy, depending on the application, drive current that has an accurate output pulsewidth relative to the pulsewidth of the input control signals is required. For example, a design in which ink that is instantly heated to a high temperature and sprayed by a nozzle is used in a so-called inkjet printer to apply ink to printing paper. As the printed dots become finer, higher precision is required to control the timing for spraying the ink. For this reason, in drive circuits for heating ink, high-precision pulse signals must be output for the input pulse control signals.
For such a drive circuit, in addition to circuits that use existing bipolar transistors, drain output type drive circuits that use a high breakdown voltage NMOS have been proposed.
FIG. 5
is a circuit diagram showing one example of such a drive circuit. This drive circuit is constituted with PMOS transistors QP
1
and QP
2
, NMOS transistors QN
1
, QN
2
and QN
3
, and inverter INV
1
, as shown.
Transistor QN
3
is a high-breakdown voltage NMOS transistor. The resistive element R
1
connected to the drain of transistor QN
3
is a load resistor. During operation, heat is generated by drive current I
L
that is output from the drain of transistor QN
3
flowing through load resistor R
1
. This heat is used to heat the ink, for example.
As shown in
FIG. 5
, in PMOS transistors QP
1
and QP
2
, the sources are connected to source voltage V
CC1
and the gates are connected to the drains of each other's transistors. The drains of NMOS transistors QN
1
and QN
2
are connected to the drains of transistors QP
1
and QP
2
, respectively, and their sources are grounded. Input signal S
in
is applied to the gate of transistor QN
1
and the inverted logic signal of input signal S
in
is applied to the gate of transistor QN
2
.
Load resistor R
1
is connected between source voltage V
CC2
and the drain of NMOS transistor QN
3
. The gate of transistor QN
3
is connected to the drain of transistor QN
2
and its source is grounded.
Source voltage V
CC1
is 15 V, for example, and source voltage V
CC2
is 20-30 V, for example. For the logic level of input signal S
in
, for example, the high level is 5 V and the low level is 0 V.
Input signal S
in
, is a pulse signal, and transistor QN
3
supplies a pulsed current signal to load resistor R
1
corresponding to this pulse signal. The operation of this drive circuit is explained below with reference to FIG.
5
.
When input signal S
in
is low, transistor QN
1
is cut off and transistor QN
2
is conducting. At this time, the drain of transistor QN
2
is held approximately at ground potential, so that transistor QP
1
conducts and transistor QP
2
cuts off. At this time, node ND
1
is held approximately at ground potential GND.
The voltage V
01
of node ND
1
is applied to the gate of transistor QN
3
, so that transistor QN
3
cuts off and no current flows to load resistor R
1
.
Next, when input signal S
in
goes from low to high, transistor QN
1
conducts and transistor QN
2
cuts off. Accordingly, transistor QP
2
conducts, so that transistor QP
1
cuts off and node ND
1
is held approximately at source voltage V
CC1
. At this time, transistor QN
3
conducts and drive current I
L
flows to load resistor R
1
. The drive current produces heat in load resistor R
1
.
As stated above, when input signal S
in
is low, transistor QN
3
cuts off and no drive current is supplied to load resistor R
1
. On the other hand, when input signal S
in
is high, transistor QN
3
conducts and drive current I
L
is supplied to load resistor R
1
. That is, the timing at which drive current is supplied to load resistor R
1
is controlled according to input signal S
in
.
In this connection, there is a large punch-through current that accompanies the switching of input signal Sin in the conventional drive circuit, and the amount of power consumed by the circuit will be high. In order to balance the output, that is, to equalize the rise time t
r
and fall time t
f
and the rise delay time t
PLH
and fall delay time t
PHL
of drive current I
L
supplied to the load resistor, the size of output transistors QP
2
and QN
2
and the magnitude of source voltage V
CC1
must be adjusted. In addition, they must be readjusted according to load conditions, such as the magnitude of source voltage V
CC2
, the resistance of load resistor R
1
, etc. Even if they are adjusted, production variations must be taken into account.
The drive circuit shown in
FIGS. 6 and 7
has been proposed to improve this situation.
As shown in
FIG. 6
, in this drive circuit, constant current sources IS
1
and IS
2
are added to the drive circuit shown in FIG.
5
. As shown in the figure, the sources of PMOS transistors QP
3
and QP
4
are connected to each other and to current source IS
1
. The supply current I
0
from current source IS
1
is input to the sources of transistor QP
3
or QP
4
.
At the same time, current source IS
2
is connected between the source and ground potential GND of transistor QN
5
. Thus, when transistor QN
5
is conducting, its source current is determined by supply current I
1
from current source IS
2
.
The drive circuit shown in
FIG. 6
operates in approximately the same way as the drive circuit shown in FIG.
5
. That is, when input signal S
in
is low, transistor QN
6
cuts off and no drive current is supplied to load resistor R
2
. On the other hand, when input signal S
in
is high, transistor QN
6
conducts and drive current I
L
is supplied to load resistor R
2
. The timing of the drive current supplied to load resistor R
2
is controlled according to input signal S
in
in this way.
FIG. 7
shows an example of another improvement to a drive circuit. As shown in the figure, transistors QP
5
and QP
6
constitute a current mirror circuit in this drive circuit. The current mirror circuit functions as a timing load circuit for transistors QN
7
and QN
8
. Resistive element R
3
is connected between the drain of transistor QP
5
and the drain of QN
7
, and resistive element R
4
is connected between the drain of transistor QP
6
and the drain of QN
8
.
This drive circuit also operates in approximately the same way as the drive circuit shown in FIG.
5
. That is, when input signal S
in
is low, transistor QN
9
cuts off and no drive current is supplied to load resistor R
5
. On the other hand, when input signal S
in
is high, transistor QN
9
conducts and drive current I
L
is supplied to load resistor R
5
. The timing of the drive current supplied to load resistor R
5
is controlled according to input signal S
in
in this way.
In the drive circuit shown in
FIG. 6
, punch-through current during switching is limited by current sources IS
1
and IS
2
. However, with this drive circuit, source voltage V
CC1
and output currents I
0
and I
1
of current sources IS
1
and IS
2
must be adjusted to balance the output, and they must also be readjusted according to load conditions, for example, the value of source voltage V
CC2
, the resistance of load resistor R
2
, etc.
And in the drive circuit shown in
FIG. 7
, punch-through current during switching is limited by resistive elements R
3
and R
4
that are connected to the drains of transistor QN
7
and QN
8
. However, like the drive circuits shown in
FIGS. 5 and 6
, the values for resistive elements R
3
and R
4
and source voltage V
CC1
must be adjusted, and in addition, readjusted, according to load conditions, for example, the value of source voltage V
CC2
, the resistance of load resistor R
5
, etc., in order to balance output.
SUMMARY OF THE INVENTION
The present invention was devised in consideration of these circumstances. Its purpose is to provide a drive circuit that makes circuit adjustment easy, that can maintain a balanced output drive current, and that can supply high precision drive curre
Brady W. James
Nguyen Long
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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