Pulse or digital communications – Spread spectrum – Direct sequence
Reexamination Certificate
2000-11-30
2004-04-20
Ghayour, Mohammad H. (Department: 2634)
Pulse or digital communications
Spread spectrum
Direct sequence
C375S143000, C375S343000
Reexamination Certificate
active
06724812
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a digital matched filter for use in, for example, a spread spectrum communication receiver.
In a so-called direct sequence spread spectrum communication system that transmits an information signal multiplied by a wide-band despreading code and restores a received signal into the original narrow-band information signal by despreading the received signal, the information signal can be detected even when the carrier-to-noise ratio of a received radio wave is degraded. Therefore, the system is full of promise for code division multiple access, which is one of multiple access schemes for mobile communication systems.
According to this direct sequence spread spectrum communication system, the spread received data is despread to be restored to the original state, and therefore, it is required to synchronize the received data with the despreading code sequence. As an index of establishing synchronization, a correlation value of the received data and a despreading code sequence is used. A sum of products of signals of the received data and the corresponding despreading codes in an arbitrary phase is called a correlation value in the phase, and of the correlation values in various phases, the correlation value in a phase where the synchronization of the received data with the despreading code sequence is established takes the maximum value.
Then, the timing of the despreading code sequence can be synchronized to the received data by detecting the phase where the correlation value is maximized. A method using a matched filter is known as one of the methods for obtaining the correlation value in each phase.
FIG. 12
shows the construction of a matched filter of a first prior art example. In
FIG. 12
, Reference numerals
201
through
208
denote delay elements (DLY) for delaying input data, and the delay elements are connected in series so that the input data are successively shifted in synchronization with the rising edge of a clock. Reference numerals
56
through
63
denote multipliers, which multiply outputs of the delay elements
201
through
208
by the values of codes
1
through
8
. In this case, the codes are made to take the value of “1” or “0”. The output of each delay element is multiplied by one in the multipliers
56
through
63
when the value of the code is 0, and the output of each delay element is multiplied by −1 when the value of the code is 1. Reference numerals
64
through
70
denote adders, and outputs from the multipliers
56
through
63
are added by these adders
64
through
70
and outputted as output data.
Now, assuming that time domains T
1
, T
2
, T
3
, . . . are delimited in correspondence with the rising or leading edge of the clock, as shown in
FIG. 13
, and that D
1
, D
2
, D
3
, D
4
, D
5
, . . . are supplied as input data, then the contents of the delay elements
201
through
208
and of codes
1
through
8
in the time domains are as shown in
FIGS. 14A and 14B
, respectively. The input data D
1
, D
2
, D
3
, . . . are sequentially shifted in the delay elements
201
through
208
, while the correlation value of the input data and a despreading code sequence of S
1
to S
8
, which is fixed for codes
1
through
8
, is calculated.
However, according to the aforementioned conventional construction, the circuit scale for the multipliers is large. In addition, the construction needs a number of multipliers equal to the number of codes in the code sequence. This leads to a problem that the circuit scale increases as the number of codes of the despreading code sequence increases and a problem that downsizing and reduction in consumption of power are hard to achieve.
As a solution to these problems, a technique using exclusive-OR circuits (referred to as ‘XOR circuits’ hereinafter) to execute operations equivalent to the multiplication has been proposed (Japanese Patent Laid-Open Publication No. HEI 9-107271).
FIG. 15
shows an example of the construction of a matched filter employing this technique. In
FIG. 15
, reference numerals
201
through
208
denote delay elements (DLY) for delaying input data, and these delay elements are connected in series so that the input data are successively shifted in synchronization with the rising edge of a clock. Reference numerals
71
through
78
denote XOR circuits, which execute an exclusive-OR operation of the outputs of the delay elements
201
through
208
and the codes
1
through
8
. In this case, the codes are made to take the value of “1” or “0”. The output of each delay element is output as it is when the corresponding code has a value of 0, while the output of each delay element is output, with each bit of the data inverted, when the code has a value of 1. Reference numeral
79
denotes an adder, which outputs the number of “1's” included in the codes
1
through
8
. Reference numerals
80
through
87
denote adders, which add the outputs of the XOR circuits
71
through
78
and the output of the adder
79
, so that the sum is supplied as output data.
In general, in order to multiply data represented by a specified number of bits by −1 using a two's complement, the bits are inverted and then one is added thereto. Thus, by inverting by XOR circuits
71
through
78
each bit of the output of the delay element
201
through
208
corresponding to the code assuming a value of 1, and then adding the value of the code of 1 via the adder
79
, operations equivalent to the multiplication of the first prior art of
FIG. 12
are achieved.
A part constructed of the XOR circuits
71
and
72
and the adder
80
, a part constructed of the XOR circuits
73
and
74
and the adder
81
, a part constructed of the XOR circuits
75
and
76
and the adder
82
and a part constructed of the XOR circuits
77
and
78
and the adder
83
are called correlation processors (C.P.)
88
through
91
. Assuming that the delay elements
201
through
208
each have a 5-bit output, then the correlation processors
88
through
91
are each constructed of a circuit shown in FIG.
16
.
In
FIG. 16
, input lines A
4
through A
0
are connected to the bits of the output of the delay element
201
or
203
or
205
or
207
, input lines B
4
through B
0
are connected to the bits of the output of the delay element
202
or
204
or
206
or
208
, an input line C is connected to the code
1
or
3
or
5
or
7
, and an input line D is connected to the code
2
or
4
or
6
or
8
. XOR circuits
92
,
93
,
94
,
95
and
96
represent the XOR circuit
71
or
73
or
75
or
77
bit by bit. These XOR circuits execute an exclusive-OR operation of the signals of the input lines A
4
through A
0
and the signal of the input line C and output signals G
4
through G
0
. XOR circuits
97
,
98
,
99
,
100
and
101
represent the XOR
72
or
74
or
76
or
78
bit by bit and execute an exclusive-OR operation of the signals of the input lines B
4
through B
0
and the signal of the input line D, outputting signals H
4
through H
0
.
The signals G
4
through G
0
and the signals H
4
through H
0
are added up in circuits
102
through
120
corresponding to the adder
80
or
81
or
82
or
83
. An AND circuit
102
and an XOR circuit
107
execute an operation of signals G
4
and H
4
, an AND circuit
103
and an XOR circuit
108
execute an operation of signals G
3
and H
3
, and an AND circuit
104
and an XOR circuit
109
execute an operation of signals G
2
and H
2
. Further, an AND circuit
105
and an XOR circuit
110
execute an operation of signals G
1
and H
1
, and an AND circuit
106
and an XOR circuit
111
execute an operation of signals G
0
and H
0
.
When the XOR circuit
107
,
108
,
109
,
110
has an output of “0”, a corresponding selector (SEL)
112
,
113
,
114
,
115
selects the output of the AND circuit
102
,
103
,
104
,
105
to produce an output. When the XOR circuit
107
,
108
,
109
,
110
has an output of “1”, the corresponding selector
112
,
113
,
114
,
115
selects the output of the selector
113
,
Sato Yuichi
Toyoyama Shinji
Birch & Stewart Kolasch & Birch, LLP
Ghayour Mohammad H.
Sharp Kabushiki Kaisha
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