System and method for improved multiplexing to a data bus

Details System and method for improved multiplexing to a data bus System and method for improved multiplexing to a data bus

1997-07-14

1998-10-13

Sheikh, Ayaz R.

395310, 39542101, 395307, G06F 1338

Patent

active

058225544

ABSTRACT:
A system and method for multiplexing the data outputs of multiple devices to a data bus using variable size multiplexers that do not require an even 2.sup.N number of inputs. This enables logical groupings of like registers to be more easily and more efficiently multiplexed together. The multiplexing system includes a plurality of registers wherein each register supplies eight bits of data to an eight-bit data bus. Register decode logic receives addresses from the bus and outputs a plurality of register select signals that select the registers during write cycles. The register select signals are also coupled with the outputs of each respective register to form an internal 9-bit bus output from each of the registers. The 9-bit bus internal output from each of the plurality of registers are coupled through one or more layers of multiplexing logic to provide an output to the eight-bit data bus. Instead of using standard 2.sup.N multiplexers with N select lines and 2.sup.N inputs, the present invention uses multiplexers of any size not necessarily a multiple of 2. The multiplexers are preferably sized based on logical groupings of like registers. Therefore, the present invention uses multiplexers which can receive any number of X inputs, where X is not necessarily a multiple of two. This allows variable size multiplexers to be used in the system, thus reducing system components and simplifying the design process.

REFERENCES:
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patent: 5543731 (1996-08-01), Sigal et al.
Mano, M. Morris, "Digital Design", Prentice-Hall Inc., NJ, pp. 166-167, 173-180, 258-264, 293-299, 1991.

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