Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-04-26
2004-04-20
Nguyen, Tan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185110
Reexamination Certificate
active
06724658
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and a circuit for generating reference voltages for reading a multilevel memory cell.
2. Description of the Related Art
As is known, the need for nonvolatile memories having increasingly larger densities has led to manufacturing multi-level memories wherein the information, stored as charge quantity in a floating-gate region, is encoded by fractionating the entrapped charge. In this way, the characteristic of a multilevel flash cell is described by a number of curves representing the pattern of the drain current Ids as a function of the gate voltage Vgs, each curve being associated to a different logic value. For example,
FIG. 1
shows the characteristic of a four-level (2-bit) flash cell which stores the bits “11”, “10”, “01” and “00”, corresponding to threshold voltages Vt
1
, Vt
2
, Vt
3
and Vt
4
.
Reading of multi-level cells is carried out evaluating the current or the voltage.
Current reading is based on comparing the current flowing in a cell at a preset gate voltage Vgs and the current flowing in a reference cell, the characteristic of which is intermediate between the distributions of the programmed cells, as shown in FIG.
2
. The comparison is made after a current-to-voltage conversion, both of the current of the cell and of the reference current.
Current reading has a number of problems, the main ones depend on parasitic resistances, such as source and drain-contact resistance of the cell, resistance of the metal connections, and resistance caused by the pass transistors of the column decoder.
As a whole, the result is a reduction in current dynamics. Consequently, the comparator that compares the voltages after current-to-voltage conversion must have a greater sensitivity. In addition, the actual characteristics differ with respect to the ideal ones, as shown in FIG.
3
. Due to such non-idealities, current reading of multilevel memory cells having more than two bits per cell is difficult, because it is required to distinguish extremely near current levels from one another.
To overcome the above problems, U.S. Pat. No. 6,034,888, in the name of the present Applicant, proposes a voltage reading method using a closed-loop circuit (see FIG.
4
). In this circuit, the current of the cell to be read is compared with a reference current, and the gate voltage of the cell is modulated until reaching the equilibrium of the system. Thereby, the gate voltage of the cell reaches a value that can be defined as the threshold value of the cell.
However, also this solution is not free from problems, due to the need for an A/D converter able to read the voltage on the gate terminal of the cell, and to the constraint of not being able to read more than one cell at a time, since the row is in common to more than one cell and cannot assume different voltage values.
The solutions devised for solving the above problems moreover involve other disadvantages (increase in read time, greater area) and in any case call for the capacity to discriminate very small currents. On the other hand, the new technologies, involving a reduction in the cell dimensions, lead in turn to a reduction in the cell current, even though solutions are known for reducing the parasitic effects that determine the losses of linearity.
BRIEF SUMMARY OF THE INVENTION
An embodiment of the present invention provides a circuit for generating reference voltages that will enable the limitations described previously to be overcome.
According to embodiments of the present invention, a method and a circuit for generating reference voltages for reading a multilevel memory cell are provided, as further defined below.
According to one embodiment of the invention, a circuit for generating reference voltages for reading a multilevel memory cell is provided, including a first reference cell and a second reference cell having, respectively, a first reference programming level and a second reference programming level. A first reference circuit and a second reference circuit are respectively connected to the first and the second reference cells and have respective output terminals which respectively supply a first reference voltage and a second reference voltage. Voltage-dividing means having a first connection node and a second connection node, respectively, are connected to the output terminals of the first and second reference circuits to receive, respectively, the first reference voltage and the second reference voltage, and additionally having a plurality of intermediate nodes supplying respective third reference voltages at equal distances apart.
Another embodiment provides a method for generating reference voltages for reading a multilevel memory cell, including reading a first memory cell and a second memory cell respectively having a first reference programming level and a second reference programming level, for generating, respectively, a first reference voltage and a second reference voltage, and generating a plurality of third reference voltages which are intermediate between the first reference voltage and the second reference voltage and are at equal distances apart.
REFERENCES:
patent: 5999454 (1999-12-01), Smith
patent: 6009022 (1999-12-01), Lee et al.
patent: 6034888 (2000-03-01), Pasotti et al.
patent: 6097635 (2000-08-01), Chang
patent: 6134147 (2000-10-01), Kaneda
patent: 6507183 (2003-01-01), Mulatti et al.
patent: 0 833 340 (1998-04-01), None
patent: WO 00/42615 (2000-07-01), None
Campardo Giovanni
Micheloni Rino
Nguyen Tan
STMicroelectronics S.r.l.
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