Excavating
Patent
1996-06-06
1999-08-17
Teska, Kevin J.
Excavating
39550036, 395381, 395387, 395568, 395572, 371 224, G06F 9445
Patent
active
059406054
ABSTRACT:
At least two test instructions are sequentially simulated. Concurrently the number of clocks taken for simulating at least two test instructions are counted. The peripheral processing program relating to at least two test instructions are simulated for the number of clocks counted after simulating at least two test instructions.
REFERENCES:
patent: 4744084 (1988-05-01), Beck et al.
patent: 5021947 (1991-06-01), Campbell et al.
patent: 5425036 (1995-06-01), Liu et al.
patent: 5450586 (1995-09-01), Kuzara et al.
patent: 5488713 (1996-01-01), Norton et al.
patent: 5517637 (1996-05-01), Bruce, Jr. et al.
patent: 5621651 (1997-04-01), Swoboda
patent: 5671402 (1997-09-01), Nasu et al.
patent: 5673425 (1997-09-01), Iwashita
O. Feger, "Simulating, testing and troubleshooting 8051/515 microcontrollers with Simula51", Siemens Components, vol. 28, No. 1, Jan. 1993, pp. 13-15.
J. Chance, "Simulation experiences in the development of software for digital signal processors", Microprocessors & Microsystems, vol. 10, No. 8, Oct. 1986, pp. 419-426.
D. Mockridge, "SIM--An 8051 Simulator", Elektor Electronics, vol. 20, No. 218, Jan. 1994, pp. 10-13.
Dawson et al., "The Verilog Procedural Interface for the Verilog Hardware Description Language", IEEE, 1996, pp. 17-23.
NEC Corporation
Phan Thai
Teska Kevin J.
LandOfFree
Simulation method and simulation system does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Simulation method and simulation system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Simulation method and simulation system will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-324021