Electricity: power supply or regulation systems – Output level responsive – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2002-11-04
2004-04-13
Berhane, Adolf (Department: 2838)
Electricity: power supply or regulation systems
Output level responsive
Using a three or more terminal semiconductive device as the...
Reexamination Certificate
active
06720754
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit voltage regulator.
2. Description of the Related Art
FIG. 2
is a block diagram showing a configuration example of a conventional voltage regulator. A source terminal and a drain terminal of a P-channel MOS transistor
1
are connected in series between an input terminal
101
and an output terminal
103
. A gate terminal of the P-channel MOS transistor
1
is connected with an output terminal of a differential amplifying circuit
10
. Respective input terminals of the differential amplifying circuit
10
are connected with an output voltage terminal of a reference voltage source
11
and an output voltage terminal of a voltage dividing circuit
12
.
The differential amplifying circuit
10
compares a voltage of the reference voltage source
11
with an output voltage of the voltage dividing circuit
12
, keeps the voltage of the output voltage terminal of the reference voltage source
11
and the voltage of the output voltage terminal of the voltage dividing circuit
12
to the same voltage, and controls a gate voltage of the P-channel MOS transistor
1
so as to keep a voltage of the output terminal
103
to be a predetermined value.
In order to limit a current value in the case where the output terminal
103
of the voltage regulator is short-circuited and to prevent the P-channel MOS transistor
1
from overheating, a P-channel MOS transistor
2
having a gate terminal and a source terminal which are common to the gate terminal and the source terminal of the P-channel MOS transistor
1
, a resistor
21
inserted between the output terminal and the drain terminal of the P-channel MOS transistor
2
, a resistor
22
connected with the input terminal
101
, and an N-channel MOS transistor
3
in which the drain terminal is connected with the resistor
22
in series are provided. The output terminal
103
is connected with the drain terminal of the N-channel MOS transistor
3
. The gate terminal of the N-channel MOS transistor
3
is connected with the drain terminal of the P-channel MOS transistor
2
. A base terminal of the N-channel MOS transistor
3
is connected with a ground terminal
102
. The drain terminal of the N-channel MOS transistor
3
is connected with a gate terminal of a P-channel MOS transistor
4
. A source terminal of the P-channel MOS transistor
4
is connected with the input terminal
101
. The drain terminal of the P-channel MOS transistor
4
is connected with the gate terminal of the P-channel MOS transistor
1
.
When a current flows into the P-channel MOS transistor
1
, a current flows into the P-channel MOS transistor
2
based on a ratio determined by a ratio of a channel length and a channel width with respect to the P-channel MOS transistor
1
and the P-channel MOS transistor
2
.
A voltage between both ends of the resistor
21
is inputted to an invert circuit composed of the resistor
22
and the N-channel MOS transistor
3
and the output of the invert circuit is inputted to the gate of the P-channel MOS transistor
4
inserted between the gate and the source of the P-channel MOS transistor
1
so that the P-channel MOS transistor
4
is turned ON/OFF. Thus, a voltage between the gate and the source of the P-channel MOS transistor
1
can be adjusted so that a value of a current flowing into the output terminal
103
can be controlled to a specified value.
Next, circuit operation will be described. If the output terminal
103
is short-circuited with the ground terminal
102
, a large current tends to flow into the P-channel MOS transistor
1
. At this time, a current which is determined by a ratio of a channel length and a channel width with respect to the P-channel MOS transistor
1
and the P-channel MOS transistor
2
flows into the P-channel MOS transistor
2
. The voltage between both ends of the resistor
21
is risen proportional to the current value. When the voltage exceeds a threshold voltage of the N-channel MOS transistor
3
, the N-channel MOS transistor
3
is turned ON and a voltage between the gate and the source of the P-channel MOS transistor
4
is increased. Thus, the P-channel MOS transistor
4
tends toward an ON state.
If the P-channel MOS transistor
4
is shifted toward an ON state, a gate voltage of the P-channel MOS transistor
1
approaches a potential of the input terminal
101
. Thus, a voltage between the gate and the source of the P-channel MOS transistor
1
becomes smaller so that it is shifted toward an OFF state. By such operation, a current flowing into the P-channel MOS transistor
1
is limited and decreased.
FIG. 3
shows a characteristic between an output current flowing into the output terminal
103
and an output current at this time. As shown in
FIG. 3
, the output current is reduced from a maximum current Im as the output voltage is reduced. Then, when the output voltage is zero, that is, the output terminal
103
is short-circuited with the ground terminal
102
, it becomes a current value of shirt circuit current Is. A mechanism by which this characteristic is realized is obtained due to the fact that a source potential of the N-channel MOS transistor
3
is different from a base potential so that a threshold voltage of the N-channel MOS transistor
3
is varied by a back gate effect. When the output voltage of the voltage regulator is reduced, the threshold voltage of the N-channel MOS transistor
3
becomes lower by a back gate effect.
When the threshold voltage of the N-channel MOS transistor
3
becomes lower by a back gate effect, even if a current flowing into the resister
21
is small, the N-channel MOS transistor
3
is turned ON. Thus, a current flowing into the P-channel MOS transistor
1
becomes smaller. Accordingly, a characteristic as shown in
FIG. 3
is obtained, which is expressed by a fixed straight line and subsequent turn-back slant line (for example, see patent reference 1).
Patent Reference: JP 07-74976 B (
FIGS. 1 and 3
)
The maximum current Im is a current used in a device connected with the output terminal
103
. Thus, it is required that this current is maximized. In addition, a short circuit current Is is a current produced at a time when the output terminal is short-circuited with the ground terminal. Thus, it is required that this current is minimized.
However, according to the voltage regulator having the above configuration, a ratio of Im and Is is dependent on a back gate effect of the N-channel MOS transistor
3
. Thus, the ratio of the maximum current Im and the short circuit current Is of the voltage regulator can not be adjusted. Accordingly, there is a problem that the maximum current cannot be made large and the short circuit current cannot be made small.
SUMMARY OF THE INVENTION
In order to solve the above-mentioned problem, according to a voltage regulator of the present invention, the configuration is used in which a resistance value for detecting an output current is changed by an output voltage and a limited current can be changed according to the output voltage.
Therefore, according to the invention of the present application, there is provided a voltage regulator for controlling a current flowing into an output voltage terminal in accordance with an output voltage, comprising:
a first MOS transistor having a first conductivity type in which a source terminal thereof is connected with an input voltage terminal and a drain terminal thereof is connected with the output voltage terminal;
a differential amplifying circuit having two input terminals in which an output terminal thereof is connected with a gate terminal of the first MOS transistor;
a first reference voltage source which is connected between one of the input terminals of the differential amplifying circuit and a ground terminal and in which an output terminal thereof is connected with the one input terminal of the differential amplifying circuit; and
a voltage dividing circuit which is connected between the output voltage terminal and the ground terminal and in which an output voltage terminal
Adams & Wilks
Berhane Adolf
Seiko Instruments Inc.
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