Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2002-05-31
2004-07-06
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S107000, C438S108000, C438S109000, C438S112000, C438S614000, C438S615000, C438S622000
Reexamination Certificate
active
06759268
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device and manufacturing method therefor, and particularly to technology useful for effectively realizing higher integration and higher functionality in a semiconductor device wherein a plurality of semiconductor elements (chips) is mounted in a single package.
2. Description of the Related Art
In
FIG. 1
are diagrammed examples of semiconductor devices of the type described above.
In the examples diagrammed, semiconductor devices are represented wherein a plurality of semiconductor chips is mounted on one substrate. In the example in
FIG. 1A
, semiconductor chips
2
are mounted on both surfaces of a substrate
1
; in the example in
FIG. 1B
, semiconductor chips
2
and
2
a
are mounted in a stacked configuration on one surface of the substrate
1
; in the example in
FIG. 1C
, a plurality of semiconductor chips
2
is mounted in a plane on the substrate
1
; and in the example in
FIG. 1D
, one semiconductor chip
2
is mounted on one surface of the substrate
1
, while a plurality of semiconductor chips
2
is mounted on the other surface thereof. These examples are respectively diagrammed schematically.
On the surface of the substrate
1
, wiring patterns are formed as appropriate. To the wiring patterns, the electrode terminals (not shown) of the semiconductor chips
2
and
2
a
are electrically connected by wire bonding. The electrical connections between the semiconductor chips and the wiring patterns are not limited to wire bonding connection, and flip chip connections or TAB connections or the like can also be used.
In a conventional semiconductor device as described above, the semiconductor chips
2
and
2
a
are mounted in a mounting surface of the substrate
1
, wherefore, due to the fact that the substrate
1
is made in regular sizes, the number of semiconductor chips that can be mounted is limited, which is a disadvantage.
When the semiconductor chips
2
and
2
a
are mounted in a stack, as diagrammed in
FIG. 1B
, the upper chip
2
must be made smaller than the lower chip
2
a
by an amount necessary for the area which is required to make the wire bonding connections. For that reason, the mounting area for the upper chip
2
becomes smaller, and there is inherently a limit to the number of chips that can be stacked.
In this case, when flip chip connections are used, there is no need to provide a region for bonding as described above, wherefore it is possible to increase the number of mounted chip as compared to the case of wire bonding connection. However, other difficulties arise instead.
With flip chip mounting, in general, solder bumps or other metal bumps (electrode terminals) are formed on the electrode pads of the semiconductor chips, and connections are effected by thermally pressing these bumps down on corresponding electrode pads on a mounting substrate such as a printed circuit board. When this method is applied to a stacked chip configuration as diagrammed in
FIG. 1B
, the upper chip
2
will be flip-chip connected to the lower chip
2
a
. In this case, it is necessary to form the electrode pads on the upper surface of the lower chip
2
a
so as to correspond with the positions of the bumps that are the electrode terminals of the upper chip
2
. Also, when stacking the chips, alignment must be effected between the bumps on the upper chip and the electrode pads on the lower chip, making the overall process complex, which is a disadvantage.
When mounting a plurality of semiconductor chips in a single package in this manner, with a method as diagrammed in
FIG. 1
in which the semiconductor chips
2
and
2
a
are simply mounted on the mounting surface or surfaces of the substrate
1
, the number of semiconductor chips that are mounted is limited, and it is not always possible to realize adequately high integration and functionality.
That being so, in terms of a method for effecting higher integration and higher functionality, semiconductor device configurations have been devised in which the substrate is made in multiple layers, and semiconductor elements are provided inside the substrate. If use is made of a multi-layer substrate structure wherein a plurality of wiring layers is provided, for example, it is possible to electrically interconnect the semiconductor chips and deploy them three-dimensionally inside the substrate. It is not necessarily easy, however, to imbed the semiconductor chips inside the substrate and form the wiring layers in multiple layers. When the recent demands for making packages smaller and lighter in weight are taken into consideration, furthermore, there are problems which must be faced, such as the necessity of forming the semiconductor devices compactly with the overall thickness thereof made thinner.
SUMMARY OF THE INVENTION
An object of the present invention, which was devised in view of such problems in the prior art, is to provide a semiconductor device, and manufacturing method therefor, with which it is possible, when mounting a plurality of semiconductor elements (chips) in a single package, to make the configuration reliable and compact, and wherewith higher integration and higher functionality can be realized more effectively.
In order to resolve the problems with the prior art stated in the foregoing, in the present invention, effective use is made of the build-up method and other multi-layer wiring technologies in which advances have been made in recent years, in terms of effecting practicality, in the field of semiconductor packaging.
A multi-layer wiring board for which the build-up method is used, for example, is generally built up by sequentially repeating a process for forming an insulating layer, a process for forming a via hole in the insulating layer, and a process for forming a conductor layer (wiring pattern) that includes the interior of the via hole. If a multi-layer wiring board obtained by such a build-up method is used, it is possible to imbed and mount semiconductor elements (chips) exhibiting enhanced integration levels, etc., in the built-up layers, and to provide electrical connection therebetween.
Accordingly, based on one aspect of the present invention, a semiconductor device is provided that comprises: a multi-layer wiring board in which conductor layers having wiring patterns formed thereon are formed in multiple layers with an insulating layer interposed therebetween and the wiring patterns are mutually electrically connected through via holes that pass through the insulating layers; and semiconductor elements that are mounted and imbedded inside each of the insulating layers of that multi-layer wiring board; wherein the semiconductor elements are electrically connected to the wiring patterns that are covered by those insulating layers, and are stacked up in a direction perpendicular to plane of the surface of the multi-layer wiring board.
More specifically, the present invention is as follows.
1. A semiconductor device comprising:
a base substrate on one surface of which wiring patterns are formed;
a plurality of insulating layers located on and above the surface thereof;
conductor layers having wiring patterns formed therein and located on the insulating layers; and
semiconductor elements imbedded and mounted inside the insulating layers; wherein:
the wiring patterns are mutually electrically connected, passing through the insulating layers; and
the semiconductor elements are electrically connected to the wiring patterns.
2. The semiconductor device described in 1 above, wherein one or more semiconductor elements are imbedded and mounted inside each of the plurality of insulating layers.
3. The semiconductor device described in 1 above, wherein two or more semiconductor elements are imbedded and mounted inside each of the plurality of insulating layers.
4. The semiconductor device described in 1 above, wherein the thickness of the semiconductor elements is 50 &mgr;m or less.
5. The semiconductor device described in 1 above, wherein the semiconductor elements and wiring patterns cor
Nguyen Khiem
Shinko Electric Industries Co. Ltd.
Staas & Halsey , LLP
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