Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2002-04-17
2004-03-02
Graybill, David E. (Department: 2827)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S129000, C438S599000, C438S612000, C438S613000, C438S666000
Reexamination Certificate
active
06699732
ABSTRACT:
BACKGROUND OF INVENTION
Flip-chip packaging generally provides a small footprint package with a large number of electric connections to a semiconductor chip.
FIG. 1A
illustrates an example of a conventional flip-chip packaged device
100
including a semiconductor chip
110
that is attached to a substrate
130
.
Semiconductor chip
110
can be any type of integrated circuit die containing active circuit elements that are electrically accessible through die pads on a surface of semiconductor chip
110
. In
FIG. 1A
, an array of solder bumps
120
on the active surface of chip
110
electrically connect to the die pads and through the die pads to the active circuitry in chip
110
, and chip
110
is flipped so that solder bumps
120
contact a top surface of substrate
130
.
Substrate
130
is typically a printed circuit made of a composite material forming a flexible or rigid carrier having conductive traces. The traces are generally made of copper or another metal and include an array of bond pads
140
. Solder bumps
120
on chip
110
electrically contact respective bond pads
140
on the top surface of substrate
130
, and the conductive traces, which extend through substrate
130
, electrically connect solder bumps
120
to solder balls
135
on the bottom surface of substrate
130
. Solder balls
135
are typically arranged in a ball grid array and form the terminals of packaged device
100
. The ball grid array can be attached to a printed circuit board or other circuitry in a product containing packaged device
100
.
Generally, bond pads
140
on substrate
130
, have a spacing that matches the spacing of solder bumps
120
of chip
110
at room temperature, so that at room temperature, the pitch of die pads on chip
110
matches the pitch of bond pads
140
on substrate
130
. Accordingly, at room temperature, all of the solder bumps
120
can be centered on respective bond pads
140
as shown in FIG.
2
A. However, at higher temperatures, a difference in the thermal expansion of semiconductor chip
110
and substrate
130
leads to a mismatch in the spacing of solder bumps
120
and pads
140
. In particular,
FIG. 2B
shows a best-case alignment of solder bumps
120
and bond pads
140
when chip
110
and substrate
130
are at an elevated temperature. In
FIG. 2B
, solder bumps
120
near the center of the array are closest to being centered with respective bond pads
140
, and solder bumps
120
near the edges of the array are significantly offset from the centers of respective bond pads
140
. The differential alignment is related to the distance of the particular bond pad
140
from the central matching points (e.g., an origin 0,0) of chip
110
and substrate
130
.
The process of attaching chip
110
to substrate
130
typically heats chip
110
and substrate
130
to a soldering temperature above the melting point of solder bumps
120
. Solder bumps
120
at least partially melt and wet corresponding bond pads
140
when the temperature reaches the soldering temperature and then resolidify to bond to corresponding bond pads
140
when the temperature drops back below the melting point of the solder. Accordingly, the bonding occurs at a high temperature where the spacing of solder bumps
120
and bond pads
140
are mismatched as illustrated in FIG.
1
C. Even with best-case alignment, electrical connections near the perimeter of the array of solder bumps
120
may be undependable because of the mismatch or smaller overlap of solder bumps
120
and bond pads
140
. Additionally, alignment of chip
110
and substrate
130
for the bonding process must be precise since any variation from the best-case alignment illustrated in
FIG. 2B
will pull some of solder bumps
120
further from the centers of respective pads
140
. The misalignment can particularly cause non-wetting or de-wetting where the melted solder fails to attach to at least some of bond pads
140
. Additionally, the misalignment can causes “snowman” structures
125
, where an extended solder structure connecting chip
110
to pads
140
is weak and subject to failure. When the package cools to room temperature, the faster shrinkage of the substrate deforms the bonds as illustrated in FIG.
3
.
The amount of mismatch between the spacing of solder bumps
120
and the spacing of bond pads
140
and the associated problems arising from the mismatch typically depend on the materials used in substrate
130
, the melting point of solder bumps
120
, and the size of the array of solder bumps
120
on chip
110
. As die size decreases and the number of terminals or solder bumps
120
required for die functionality increases, the spacing mismatch in flip-chip packages will worsen. Methods and structures for better matching of chip and substrate are thus needed.
SUMMARY OF INVENTION
In accordance with an aspect of the invention, a flip-chip packaging process forms a substrate having temperature compensated traces having a spacing that matches the spacing of solder bumps on a chip at an elevated temperature such as the melting point of the solder bumps. Accordingly, when a reflow or other high temperature process attaches the chip to the substrate, the solder bumps and traces can be better aligned and centered to provide a good contact for all solder bumps.
One specific embodiment of the invention is a device including a chip and a substrate. The chip has terminals (e.g., solder bumps) that are electrically connected to respective contact areas (e.g., bond pads) of conductive traces of the substrate. The spacing of the contact areas on the substrate differs from the spacing of the terminals on the chip when the chip and substrate are at room temperature, but the spacing of the contact areas on the substrate matches the spacing of the terminals on the chip when the chip and substrate are at an elevated temperature.
The elevated temperature can be approximately equal to the temperature at which the terminals are bound to respective contact areas. In particular, when the terminals use solder in bonds to the contact area, the elevated temperature can be the melting point of the solder or slightly higher. Alternatively, the elevated temperature can be selected to minimize stress in the bonds between the terminals and the contact areas. In particular, the elevated temperature can be at the center of a temperature cycle range for the chip or in an expected operating temperature range for the chip. Accordingly, the bonds are stress free at the center of the thermal cycle range or the operating temperature range. In either case, the matching of the terminals and contact areas at the elevated temperature improves the match or alignment at the bonding temperature in addition to reducing stress during operation of the package.
Another embodiment of the invention is a method for fabricating a flip-chip package. The method includes aligning a chip with a substrate, heating the chip and substrate to an elevated temperature where centers of terminals on the chip align with centers of corresponding contact areas of traces on the substrate, and bonding the terminals to the corresponding contact areas at a bonding temperature. In alternative embodiments, the elevated temperature is about equal to the bonding temperature (e.g., about equal to a melting temperature of solder used to bond the terminals and contact areas), or the elevated temperature is selected to reduce thermal stress on bonds between the terminals and the contact areas. The elevated temperature can be about equal to the middle of a temperature range expected during use of the flip-chip package or equal to an operating temperature of the flip-chip package.
REFERENCES:
patent: 6118182 (2000-09-01), Barrow
patent: 6310403 (2001-10-01), Zhang et al.
Celerity Research Pte. Ltd.
Graybill David E.
Millers David T.
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