Coded data generation or conversion – Digital code to digital code converters – Coding by table look-up techniques
Reexamination Certificate
2003-02-10
2004-01-13
Young, Brian (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
Coding by table look-up techniques
C341S050000
Reexamination Certificate
active
06677867
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data conversion circuit for converting intended input data into output data using a look-up table for conversion which defines correspondence between input and output, and a technique associated with the same.
2. Description of the Background Art
In the field of image processing, output data is sometimes created by correcting input data, and in such a situation, correspondence of output data to the input data is used as correction data while referring to a reference table for data conversion which is called a look-up table (LUT: look-up table for conversion).
This look-up table is provided in an internal memory called a LUT memory (look-up table storage memory) in a digital camera, for example. In the case where input signals obtained from charge coupled devices (CCD) used in this digital camera are used in their linear characteristics, as for the dynamic range, it is difficult to completely realize ideal dynamic range because of the internal settings of the digital camera and restrictions of video output format. For this reason, signals having levels higher than the saturation level 100IRE of the RS-170 format, for example, are truncated. In such a case, for the purpose of executing the preprocessing at high speed inside the digital camera by fully using the dynamic range of the input signal, a &ggr; conversion look-up table is used.
Now referring to
FIG. 9
, a general &ggr; conversion look-up table
3
will be described. In the &ggr; conversion look-up table
3
, memory cells (word)
8
which are in number corresponding to the number of bits of input data In are prepared, and a data size (bit depth) of each memory cell
8
corresponds to the number of bits of output data Out. In the example of
FIG. 9
, input data In of 10 bits is inputted and 8-bit output data is outputted. In this case, as the input data In is inputted into the &ggr; conversion look-up table
3
, a value of 10 bits of this input data In (that is, 2
10
patterns or values of 0 to 1023: hereinafter referred to as “word number”) is addressed, a memory cell
8
having the address of this value is selected, and 8-bit data of the memory cell
8
thus selected is outputted as output data Out.
Conventionally, a complete look-up table should be configured by a LUT memory, however, as shown in
FIG. 10
, for example, when &ggr; conversion of image data is to be conducted by using the &ggr; conversion look-up table
3
where both of the input data In and output data Out are required to be 16 bits, the word number of memory cells
8
having a bit depth of 16 bits becomes as large as 2
16
=65536, which makes the circuit scale extremely large.
In consideration of the above, Japanese Patent Application Laid-Open No. 11-252372, for example, discloses a technique which effectively uses a look-up table. In this technique, as shown in
FIG. 11
, data “A” which is input data Din of 12-bit line and data “A+1” obtainable by adding “1” to the data “A” by an adder (INC)
1
are yielded, and data of upper 10-bit lines from these 12-bit line data (“A”/“A+1”) are switched by a multiplexer (MUX)
2
for outputting to three &ggr; conversion look-up tables (LUT)
3
a
to
3
c
for three colors, R, G and B. Then outputs (8-bit data) from the respective color components of these &ggr; conversion look-up tables
3
a
to
3
c
are sequentially switched and selected by a color selecting multiplexer
4
, and data DA thus selected is outputted to an interpolation arithmetic circuit
5
and a latch circuit
6
.
At the latch circuit
6
, the data DA is latched and a resultant data DB (B=A+1) is outputted to the interpolation arithmetic circuit
5
. In other words, since the data DA and the data DB are inputted to the interpolation arithmetic circuit
5
in synchronization with each other owing to the latch at the latch circuit
6
, data in the &ggr; conversion look-up tables
3
a
to
3
c
is fetched in a timely-overlapped manner.
Then the interpolation arithmetic circuit
5
receives at its input, data for lower 2 bits of the input data Din (that is, 12 “bits”−10 “upper bits”) in addition to the above 8-bit data DA and DB, determines an interpolation ratio P in accordance with the data of lower 2 bits, executes the calculation of DA+(DB−DA)×P, and outputs the calculation result as output data Dout.
In this manner, according to the conventional technique, since a &ggr; conversion can be conducted with respect to input data whose bit number is larger than the bit depth of each memory cell (word) of the look-up table, output data Out having a sufficient bit number can be outputted even by using the LUT memories
3
a
to
3
c
having relatively small memory sizes.
Even with such a conventional technique, the bit length of output data Out is restricted by the bit depth of the respective &ggr; conversion look-up table
3
a
to
3
c,
which disabled the &ggr; conversion where the bit lengths of input and output are the same to be conducted.
SUMMARY OF THE INVENTION
In view of the above, it is an object of the present invention to provide a data conversion circuit which is able to realize a conversion output with a fineness superior to the bit depth of the LUT memory by using a LUT memory of less memory size, and related arts.
The present invention provides a data conversion circuit for converting intended input data into output data using a look-up table for conversion which defines correspondences between input and output, the data conversion circuit including: an adder for adding “1” to first table input data which is upper bit data having a bit length corresponding to an input format of the look-up table for conversion among the input data, to yield second table input data; a look-up table storage memory storing the look-up table for conversion, for outputting first table output data associated with the first table input data using the look-up table for conversion, as well as outputting second table output data associated with the second table input data using the same the look-up table for conversion; and a weighting operation part for performing a weighting operation on the first table output data and the second table output data based on lower bit data excluding the predetermined bit number of upper bit data among the input data, interpolating between each of the table output data, and calculating output data having a bit length which is longer than that of the first table output data and the second table output data, wherein the look-up table storage memory is a dual port memory to which the first table input data and the second table input data are inputted simultaneously, and from which the first table output data and the second table output data are outputted simultaneously.
According to this, it is possible to obtain output data with a fineness superior to the bit depth of the look-up table storage memory while reducing the bit depth and word number of the look-up table storage memory as small as possible.
In this case, since the look-up table storage memory is a dual port memory to which the first table input data and the second table input data are simultaneously inputted and from which the first table output data and the second table output data are simultaneously outputted, it is possible to efficiently input two sets of table input data and to efficiently output two sets of table output data. Therefore, it is possible to achieve efficient data conversion.
In another aspect of the present invention, there is provided a data conversion circuit for converting intended input data into output data using a look-up table for conversion which defines correspondences between input and output, the data conversion circuit including: an adder for adding “1” to first table input data which is upper bit data having a bit length corresponding to an input format of the look-up table for conversion among the input data, to yield second table input data; a look-up table storage memory which is a single port memo
Mega Chips Corporation
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Young Brian
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