Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2003-04-24

2004-09-21

Cuneo, Kamand (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S763010, C714S724000

Reexamination Certificate

active

06794891

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit (IC) provided with a test circuit.
FIG. 2
is a configuration diagram for showing one example of a semiconductor IC provided with a conventional test circuit.
This semiconductor IC is provided with input terminals
11
-
14
for receiving a test command etc. The input terminals
11
and
12
are provided to receive an 11-bit address signal AD and 16-bit data DT in parallel respectively, while the input terminal
13
is provided to receive a mode signal MD which performs switching between a test operation and an ordinary operation. The input terminals
11
-
13
are connected to a control unit
21
which controls this entire semiconductor IC.
The input terminal
14
, on the other hand, is provided to receive a clock signal CK having a frequency required for the test operation and the ordinary operation, to which input terminal
14
are there connected a multiply unit
22
and a terminal B of a selector (SEL)
23
. The multiply unit
22
is comprised of a Phase Locked Loop (PLL) etc., for multiplying a frequency (for example, 8 MHz) of the clock signal CK applied in the ordinary operation mode by, for example, eight to provide a frequency of 64 MHz. The output of the multiply unit
22
is connected to a terminal A of the selector
23
.
In response to the mode signal MD provided at its terminal S, the selector
23
selectively outputs a signal of either one of the terminals A and B, in such a manner that the signal of the terminal A would be selected when an ordinary operation is specified and that of the terminal B would be selected when a test operation is specified by this mode signal MD. The signal thus selected by the selector
23
is provided as a clock signal CLK to the control unit
21
.
To the control unit
21
are there connected via an internal bus
30
a test-subject function block
31
, a Random Access Memory (RAM)
32
, a Read Only Memory ROM (ROM)
33
, and other function blocks
34
,
35
, . . . The RAM
32
, ROM
33
, and the function blocks
31
,
34
, . . . are supplied with the clock signal from the selector
23
. Furthermore, the outputs of the test-subject function block
31
, the RAM
32
, and the ROM
33
are connected respectively to output terminals
101
,
102
, and
103
for outputting a 16-bit test result signal therefrom.
The following will describe the operations.
In this semiconductor IC, to conduct an operation confirmation test on the function block
31
, the RAM
32
, and the ROM
33
, a test apparatus is connected to the input terminals
11
-
14
and output terminals
101
-
103
, to supply the mode signal from the input terminal
13
in order to specify a test operation. In such a manner, the control unit
21
is set into a test operation mode and, furthermore, the terminal B is selected by the selector
23
.
Next, the clock signal CK having a frequency of 64 MHz is supplied from the input terminal
14
, so that in synchronization with this clock signal CK, the address signal AD and the data DT are provided in parallel from the input terminals
11
and
12
respectively. These address signal AD and data DT thus provided in synchronization with the clock signal CK are taken into the control unit
21
, in which these signals are given through the internal bus
30
to the function block
31
etc. A processing result of the function block
31
and data items read out from the RAM
32
and the ROM
33
are output in parallel from the output terminals
101
-
103
respectively.
The test apparatus can check the processing result and the data thus output from the output terminals
101
-
103
to confirm whether the function block
31
, the RAM
32
, and the ROM
33
are operating properly.
The semiconductor IC, on the other hand, is used in the ordinary operation mode after its functions are confirmed. In the ordinary operation mode, it is supplied at its input terminal
13
with the mode signal MD which specifies an ordinary operation and at its input terminal
14
with the clock signal CK having a frequency of 8 MHz. In such a manner, the control unit
21
is set into the ordinary operation mode and also the terminal A is selected by the selector
23
. Then, the clock signal CLK having a frequency of 64 MHz obtained as a result of multiplication at the multiply unit
22
is supplied to the control unit
21
, the respective function blocks
31
,
34
, . . . , the RAM
32
, and the ROM
33
. Based on programs and data stored in the ROM
33
, the control unit
21
performs predetermined processing.
In such a manner, in the test operation mode, without using the multiply unit
22
, the clock signal CK is directly supplied from the input terminal
14
to the control unit
21
and the function block
31
etc. It is thus possible to conduct an operation test at an arbitrary timing without taking into account operation stabilization time or a shift in phase which are caused by the multiply unit
22
.
The conventional semiconductor IC, however, has the following problems.
The high-speed clock signal CK which is originally to undergo frequency multiplication at the multiply unit
22
and be supplied needs to be supplied from the outside via the input terminal
14
and, furthermore, it is necessary to input the address signal AD and the data DT in synchronization with this clock signal CK from the input terminals
11
and
12
respectively and also to externally monitor signals indicative of the operation results output from the output terminals
101
-
103
, thus making it difficult to adjust the timing. Furthermore, the signals are input and output respectively from the input terminals
11
and
12
and the output terminals
101
-
103
in parallel, thus giving rise to a problem that a number of external terminals are necessary.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a semiconductor IC which can solve the above-mentioned problems of the conventional technologies, to facilitate timing adjustment in a test operation mode and reduce the number of external terminals.
To solve the above-mentioned problems, claims
1
-
11
of the invention provide a semiconductor IC having a plurality of function blocks and a control unit which controls the function blocks in accordance with a predefine program in an ordinary operation mode and tests a test-subject function block in accordance with a supplied command in a test operation mode, comprising a decision unit which, in the test operation mode, comparing data which is output from the test-subject function block in response to the command and expected value data which is provided corresponding to the command to each other in order to decide acceptability of a function of the function block and an output unit which holds a decision result given by the decision unit and outputs the decision result to an output terminal.
The semiconductor IC according to any one of claims
1
-
11
of the invention is constituted as described above and so has the following actions in the test operation mode.
For example, a test command and expected value data which corresponds to the command are provided as serial data from the outside and then converted into parallel data and stored in an instruction storage unit, from which the command is read out by the control unit so that a test-subject function block may be tested in accordance with the command. Data which is output from the test-subject function block in response to this command is compared to the expected value data at the decision unit, to decide acceptability of a function of the function block. A decision result given by the decision unit is held in the output unit and output to the output terminal.
Claims
12
-
15
of the invention provide a semiconductor IC having a plurality of function blocks including a memory and a control unit which controls the function blocks in accordance with a predefined program in an ordinary operation mode and tests a test-subject function block in accordance with a supplied command in a test operation mode, comprising a delay unit which delays a

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