Electrical computers and digital processing systems: multicomput – Computer-to-computer data routing – Least weight routing
Reexamination Certificate
2000-01-04
2004-07-06
El-Hady, Nabil (Department: 2154)
Electrical computers and digital processing systems: multicomput
Computer-to-computer data routing
Least weight routing
C709S241000, C709S201000, C711S005000, C711S129000, C711S147000, C711S148000, C711S151000, C711S153000, C711S157000, C711S202000, C712S028000
Reexamination Certificate
active
06760743
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of computer memory, with particular attention to that portion of a computer memory system that receives and delivers instructions for multiple processors.
2. Description of Related Art
Embedded processors provide a flexible means for implementing complex functions in computer hardware. The demands of high speed networking systems often require several processors running concurrently to maintain network throughput and low latency. These processors provide a pooled resource with each processor working on separate data frames, cells, or messages. This activity may be further subdivided into disjoint procedures such as inbound traffic, outbound traffic, and control traffic processing. Since the proportion of each of these traffic types can vary dynamically, each of the processors would ideally be able to perform the tasks of all traffic types. In a classic implementation of such a multiprocessor resource, each processor would have its own memory to store instructions. While this approach is acceptable for systems implemented with a couple of processors, it becomes quite expensive for systems with a large number of processors.
As an alternative approach, all of the instructions from all processors in a system can be consolidated into one memory array which is shared with all of the processors. This results in a savings in memory redundancy, but with increased latency, requiring some processors to be queued to wait their turn for receipt of data, particularly during periods of peak contention.
BRIEF DESCRIPTION OF THE INVENTION
It is an object of the present invention to satisfy the instruction requests of a plurality of processors in an optimum manner.
Another object of the present invention is to reduce the amount of instruction storage by consolidating instructions in more than one memory array, in an arrangement that will facilitate retrieval of memory segments in a rapid and efficient manner.
Yet another object is to increase instruction bandwidth to simultaneously and rapidly allow the performance of a plurality of disjoint tasks.
Still another object of the invention is to eliminate the need to store instructions in the memory of each processor.
These and other objects will become self evident in light of the disclosure of the invention as herein described.
The present invention relates to a computer instruction memory system and method for handling instructions for multiple processors. The system comprises a plurality of memory arrays corresponding to a number of disjoint tasks to be performed. A separate data path and data address is provided for each memory array. Means are included for consolidating identical instruction codes for a given disjoint task into one or more memory arrays. Means are also employed to share all of the instruction codes from the memory arrays with all of the processors.
The disjoint tasks include inbound traffic and outbound traffic. Instructions for each of these tasks are stored in duplicate in multiple memory arrays. The disjoint tasks also include a code for control tasks, and this code is stored in a separate memory. All requests for control task instructions are received by the first arbiter which services these requests and controls a first multiplexor. The multiplexor passes the address of the serviced control instruction request to a single memory array. A second arbiter receives and services all requests for inbound task instructions and controls a second multiplexor and third multiplexor in order of priority. The second multiplexor passes the address of the first serviced inbound instruction request to the second memory array. Likewise, the third multiplexor passes the address of the second serviced inbound instruction request to the third memory array. A third arbiter receives and services all requests for outbound task instructions and controls a fourth multiplexor and fifth multiplexor in order of priority. The fourth multiplexor passes the address of the first serviced outbound instruction request to a fourth memory array and the fifth multiplexor passes the address of the second serviced outbound instruction request to a fifth memory array.
The system further includes an instruction address divided into code segments. These segments are implemented with separate arrays and arbitration. Each code segment corresponds to one of the disjoint tasks to be performed.
The system further includes interleaved memory arrays. These can be used, for example, for carrying out a reporting task. For this, the system uses a fourth arbiter and a fifth arbiter that are adapted to receive and service all requests for disjoint task instructions stored in the interleaved arrays. The fourth arbiter controls a sixth multiplexor and the fifth arbiter controls a seventh multiplexor on the order of priority. The sixth multiplexor passes the address of the serviced instructions from the fourth arbiter to a sixth memory array, and the seventh multiplexor passes the address of the serviced instructions from the fifth arbiter to a seventh memory array.
The invention further includes a computer instruction memory system having increased memory bandwidth and a method for increasing the memory bandwidth of a computer instruction memory system. This is achieved by segmenting the instruction address space into separate code segments. Each address space is implemented with separate memory arrays and arbitration. One disjoint task is assigned to each of the code segments. Certain of the instruction address segments having high processor contention are provided with two memory arrays with duplicate content. An arbiter then arbitrates service requests from the processors, to each memory array. Separate data address and data paths are provided for each memory for decreased latency.
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Heddes Marco C.
Rinaldi Mark Anthony
Youngman Brian Alan
Driggs Lucas Brubaker & Hogg Co. L.P.A.
El-Hady Nabil
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