Multi-layer capacitor and method for producing the same

Details Multi-layer capacitor and method for producing the same Multi-layer capacitor and method for producing the same

2003-10-08

2004-09-21

Dinkins, Anthony (Department: 2831)

Electricity: electrical systems and devices

Electrostatic capacitors

Fixed capacitor

C361S306100, C361S321100, C361S321500, C361S311000, C361S313000

Reexamination Certificate

active

06795295

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a multi-layer capacitor.
2. Description of the Related Art
Recent implementation of high-speed ICs in the field of information and communications technology, typified by digital circuits used in computers and radio transmission, is striking. However, such attainment of high speed and high degree of integration for ICs involves an increase in high-frequency noise, which causes equipment malfunction, and thus raises a serious problem. The high-frequency noise is caused by a drop in supply voltage resulting from simultaneous switching of logic devices. In order to reduce the high-frequency noise, a capacitor for supplying energy to a power supply, or a so-called decoupling capacitor, has been used.
In order to achieve instantaneous supply of large energy, the decoupling capacitor is required to have a large capacitance and a low inductance (ESL). These characteristics mainly depend on the internal structure of a capacitor, and various internal structures have been proposed.
In the case of handling high-frequency waves and high-speed pulses, a conductor line that connects an electronic component mounted on a wiring board to a power supply for supplying operating power to the electronic component imparts excess inductance. An increase in an inductance component of a conductor line increases the difficulty of attaining stable supply of operating voltage. Furthermore, superposition of noise on a conductor line causes malfunction of an electronic component. The above-mentioned implementation of high frequency and a high degree of circuit integration increases occurrence of such a problem. In order to shorten the length of a conductor line extending between a capacitor and a power supply for the purpose of reducing an excess inductance component, a capacitor is proposed in which electrode terminals are formed on only one main surface of a capacitor body.
Existing multi-layer capacitors of the above-mentioned type include a multi-layer capacitor as described below (refer to, for example, Japanese Patent Application Laid-Open (Kokai) No. 5-347227). The multi-layer capacitor includes a capacitor body formed by the steps of alternately laminating dielectric layers and internal electrode layers, and firing the resultant laminate. The multi-layer capacitor is characterized as follows: each of the internal electrode layers includes a first internal electrode layer and a second internal electrode layer that face each other by mediation of a dielectric layer; a first electrode terminal and a second electrode terminal are formed on one main surface of the capacitor body; a first via electrode is formed in the capacitor body so as to extend in the lamination direction of the capacitor body and to connect the first electrode terminal and the first internal electrode layers; and a second via electrode is formed in the capacitor body so as to extend in the lamination direction of the capacitor body and to connect the second electrode terminal and the second internal electrode layers. The facing first and second internal electrode layers function as a capacitor unit, which is the minimum unit that forms a capacitance. The capacitor units are connected in parallel by the first and second via electrodes.
Another known mode of the above-described multi-layer capacitor includes a plurality of first and second via electrodes and a plurality of first and second electrode terminals corresponding to the via electrodes, the plurality of first and second via electrodes being arrayed in a grid.
Recent implementation of ICs (integrated circuits) of high speed and high degree of integration requires a further reduction in the ESL (equivalent series resistance) of a capacitor and reduction in size with high electrical and mechanical reliability without involving a reduction in the capacitance thereof.
SUMMARY OF THE INVENTION
The present invention has been achieved to solve the aforementioned problems or rather to meet future requirements for multi-layer capacitors, and an object of the present invention is to reduce the ESL of a multi-layer capacitor. Another object of the present invention is to provide a multi-layer capacitor including a ceramic capacitor having high electrical and mechanical reliability.
In a first aspect of the invention, as will be understood by reference to FIG.
13
(A) or FIG.
14
(A), the above objects of the present invention have been achieved by providing (1) a multi-layer ceramic capacitor (
100
) comprising:
a plurality of dielectric ceramic layers (
120
), each having first and second layer planes;
a plurality of first internal electrodes (
130
a
) provided on the first layer planes of the dielectric ceramic layers (
120
) and a plurality of second internal electrodes (
130
b
) provided on the second layer planes of the dielectric ceramic layers (
120
), the dielectric layers (
120
) being sandwiched by the first and second internal electrodes (
130
a
,
130
b
); and
a plurality of first and second columnar electrodes (
140
a
,
140
b
) penetrating the dielectric ceramic layers (
120
) in a direction normal to the layer planes of the ceramic layers (
120
), the first columnar electrodes (
140
a
) being electrically connected to the first internal electrodes (
130
a
) and the second columnar electrodes (
140
b
) being electrically connected to the second internal electrodes (
130
b
),
wherein the first and second columnar electrodes(
140
a
,
140
b
) each has a corrugation including smaller diameter portions (
1038
a
,
1038
b
) and larger diameter portions (
1037
a
,
1037
b
),
wherein the first internal electrodes(
130
a
) are electrically connected to the first columnar electrodes (
140
a
) at larger diameter portions (
1037
a
) of the first columnar electrodes and the second internal electrodes (
130
b
) are electrically connected to the second columnar electrodes (
140
b
) at smaller diameter portions (
1037
b
) of the second columnar electrodes, and
wherein circumferential edges (
1026
a
,
1026
b
) of the dielectric ceramic layers (
120
) intrude into the first and second columnar electrodes (
140
a
,
140
b
) at the smaller diameter portions (
1038
a
,
1038
b
) of the first and second columnar electrodes (
140
a
,
140
b
).
The present invention also provides the following aspects and preferred embodiments.
(2) The multi-layer ceramic capacitor (
100
) as described in (1), wherein a plurality of first and second holes (
200
a
,
200
b
) penetrating said dielectric ceramic layers (
120
) are formed by laser and said first and second columnar electrodes (
140
a
,
140
b
) are embedded respectively in the first and second holes (
200
).
(3) The multi-layer ceramic capacitor as described in (1), wherein said circumferential edges (
1026
a
,
1026
b
) are rounded or tapered by laser (shown as rounded or tapered portions
1035
a
,
1035
b
). Since the circumferential edges (
1026
a
,
1026
b
) of the dielectric ceramic layers(
120
) are rounded or tapered, the larger diameter portions(
1037
a
,
1037
b
) of the columnar electrodes (
140
a
,
140
b
) become flange-like connecting portions (
1036
a
,
1036
b
) advantageously tapering toward the internal electrodes (
130
a
,
130
b
) and electrically connecting to the internal electrodes (
130
a
,
130
b
).
(4) The multi-layer ceramic capacitor as described in (1), wherein a difference in diameter between the larger diameter portions and the smaller diameter portions is more than a thickness of the dielectric ceramic layer (
120
), the thickness being defined as the distance between the first and second internal electrodes (
130
a
,
130
b
) sandwiching the dielectric layer (
120
).
(5) The multi-layer ceramic capacitor as described in (1), wherein said columnar electrodes (
140
a
,
140
b
) have an aspect ratio of more than 4, the aspect ratio defined as a value of the length of a given columnar electrode divided by the smallest diameter of the smaller diameter portions of the columnar electrode.
(6) The multi-layer ceramic capacitor as described in (1), wherein said

Affiliated with

Also associated with

Rating

Multi-layer capacitor and method for producing the same does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-layer capacitor and method for producing the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-layer capacitor and method for producing the same will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3235360