Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Incorporating resilient component
Reexamination Certificate
2003-02-27
2004-07-06
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Incorporating resilient component
C438S457000, C438S528000
Reexamination Certificate
active
06759277
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to the fabrication of integrated circuit (IC) devices and, more particularly, to the assembly of thin sheets of single crystal silicon onto substrates.
2. Description of the Related Art
The use of substrate materials other than silicon is of interest, as it would enable the realization of new display products that are not otherwise feasible to make. For example, there is broad agreement in the flat panel display (FPD) industry that system-on-glass (SOG) technology is a natural evolutionary step for FPDs, especially for mobile devices. As an example of this evolution, improvements in liquid crystal display (LCD) technology create a need for high performance thin film transistor (TFT) driver components on transparent substrates such as glass and polymer. In fact, SOG is a natural confluence of display and microprocessor evolution, because integration is a proven solution for greatly reducing costs while improving the compactness and reliability of electrical systems.
Another aspect of interest is flexibility, the ability of a microsystem to bend, conform, or maintain its integrity under external “stress”. These attributes would enable the manufacturing of a variety of one-use products and/or the manufacturing of robust products that maintain their functionality under a wide range of external, “environmental” conditions. Therefore, there is motivation to develop microsystems or products that use TFT microelectronic devices that are robust, have high performance, and are cheap to make.
Low-temperature polysilicon (LTPS) technology uses a laser beam to crystallize amorphous silicon and form thin polycrystalline silicon layers, also referred to as polysilicon layers. Display drivers and analog-to-digital converters for SOG devices can be formed in this manner. Unfortunately, this approach remains relatively expensive for LCD production. Moreover, polysilicon TFTs formed by LTPS technology may not provide the capability to realize sophisticated functions like central processor unit (CPU) operations and digital signal processing. Finally, the steadiness of drive currents produced by polysilicon TFTs may be inadequate for organic light emitting diode displays (OLEDs).
It would be advantageous if a process could inexpensively use SOG technology to produce TFTs able to implement sophisticated functions like CPU and digital signal processing.
It would be advantageous if a process could inexpensively use SOG technology to produce TFTs with drive currents sufficient for OLEDs.
It would be advantageous if a process could inexpensively produce TFT microelectronic devices on flexible substrates.
SUMMARY OF THE INVENTION
The present invention describes an array of crystalline silicon dies with thicknesses of 20 nanometers (nm) or more on a substrate with an area of up to two square meters. The present invention also describes a method for yielding the above-mentioned array. The present invention is accomplished using rapid thermal breakage of a crystalline silicon wafer, rapid mechanical placement of the dies on the substrate, and intermolecular bonding of the dies to the substrate. The present invention allows the formation of integrated circuit devices, such as thin film transistors, on transparent or flexible substrates.
Accordingly, a method is provided for assembling crystalline semiconductor thin film sheets onto substrates. The method delineates an array of die areas on a crystalline semiconductor wafer and implants the die areas with hydrogen ions. Then, the die areas are overlain with a layer of polymer to form, for each die, an aggregate including a polymer layer and a die area wafer first layer. An optically clear carrier is polymerically bonded to the die areas and the crystalline wafer is thermally annealed to induce breakage in the wafer. For each die, a wafer second layer with a thickness less than the die thickness is formed and, for each die, the wafer second layer is conformably attached to a substrate using intermolecular bonding.
The wafer second layer can be attached to a substrate with an area of up to approximately two square meters and the wafer second layer can have a thickness of greater than or equal to approximately 20 nm.
The wafer second layer can be conformably adapted to a substrate interface surface with a concavity or curvature. In some aspects of the method, the substrate is transparent, such as a glass substrate. In some aspects, the substrate is flexible, such as a plastic substrate.
Additional details of the above-described method and an array of crystalline silicon dies on a substrate are presented in detail below.
REFERENCES:
patent: 6194291 (2001-02-01), DiStefano et al.
patent: 6228686 (2001-05-01), Smith et al.
patent: 6387829 (2002-05-01), Usenko et al.
patent: 6627478 (2003-09-01), Smith et al.
Holmes et al., “Laser-assisted assembly for hybrid microelectromechanical systems”, Laser Microfab—ICALEO 2000, pp. D1-D9.
Droes Steven R.
Flores James S.
Takafuji Yutaka
Chaudhari Chandra
Rabdau Matthew D.
Ripma David C.
Sharp Laboratories of America Inc.
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