Semiconductor device manufacturing: process – With measuring or testing – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2002-05-15
2004-04-13
Kielin, Erik J. (Department: 2813)
Semiconductor device manufacturing: process
With measuring or testing
Packaging or treatment of packaged semiconductor
C438S612000
Reexamination Certificate
active
06720195
ABSTRACT:
TECHNICAL FIELD
This invention relates to the manufacture of microelectronic components. More particularly, aspects of the invention provide methods and apparatus for enhancing quality control in a microelectronic component manufacturing operation.
BACKGROUND
Microelectronic devices are commonly assembled by coupling together two or more microelectronic components. Some of these microelectronic components may comprise single, unpackaged semiconductor dies which are electrically coupled to other components of the microelectronic device, e.g., attaching the die to a printed circuit board (PCB) or other substrate using wire bonding or flip chip techniques.
Increasingly, packaged microelectronic components are being used to assemble larger microelectronic devices. Packaged microelectronic components typically comprise one or more semiconductor dies, a lead frame that is coupled to the die or dies, and an encapsulant that commonly encapsulates the semiconductor die(s) and a portion of the lead frame. One example of such a packaged microelectronic component and suitable methods of manufacture are disclosed in U.S. Pat. No. 5,304,842, the entirety of which is incorporated herein by reference. Other packaged microelectronic components may include small conductive pads instead of a lead frame, with the conductive pads being exposed and permitting the encapsulated die or dies to be electrically coupled to a PCB or other microelectronic component.
Such packaged microelectronic components are commonly mass-produced and subsequently assembled into larger microelectronic devices. One technique for electrically coupling packaged microelectronic components to other components of a microelectronic device employs a solder applied to the leads or conductive pads of the packaged microelectronic component prior to assembly with the rest of the device. The solder is commonly applied using electrolytic or electroless plating processes. Each of the solder-bearing microelectronic components may then be juxtaposed with a PCB or other microelectronic component, with the solder-bearing contacts of the packaged microelectronic components aligned with corresponding contacts on the PCB. The entire microelectronic device (including the packaged microelectronic component and the PCB) may then be heated to an elevated temperature at which the solder will flow, electrically coupling and physically connecting the packaged microelectronic component to the PCB. This technique, commonly referred to as a solder reflow process, is widely used in commercial manufacture of microelectronic devices. Solder reflow processes avoid the need to precisely apply separate balls of solder to a number of specific locations on a PCB on a one-by-one basis. This enhances throughput of a microelectronic device manufacturing operation. The heating required to reflow the solder can cause some other difficulties, though.
Most packaged microelectronic component manufacturers test each packaged microelectronic component before shipping it to a customer. This helps the customer minimize production losses and costs for remanufacturing devices including defective components. Experience has demonstrated that some packaged microelectronic components that meet all relevant performance criteria when the component manufacturer ships them do not perform properly in the assembled microelectronic device. It is believed that many of these “infant mortalities” can be attributed to the thermal stress placed on the packaged microelectronic component during the solder reflow operation. The various elements of the packaged microelectronic component often have different coefficients of thermal expansion (CTEs). For example, the CTE of the encapsulant may be materially different from the CTE of the semiconductor die or dies, and the lead frame and associated bonding wires may have CTEs that are different from the CTE of the encapsulant or the die. The relatively rapid temperature changes of the solder reflow process may induce stresses that cause a previously functional packaged microelectronic component to fail.
Testing procedures utilized by packaged microelectronic component manufacturers often employ an elevated temperature for an extended period of time. Such a “burn-in” process can weed out some components that would otherwise have failed over time during use. However, the maximum temperature of the testing process must be significantly lower than the reflow temperature of the solder to avoid damaging the finish of the solder. This can be an even greater problem with advanced multi-layer solders, e.g., the solder suggested in U.S. Pat. No. 5,470,787, the entirety of which is incorporated herein by reference. Typically, burn-in temperatures are less than 150° C., frequently less than 125° C. As a consequence, the thermal stresses induced in the solder reflow process can be significantly higher than thermal stresses which can be generated in a burn-in testing process without damaging otherwise acceptable packaged microelectronic components.
REFERENCES:
patent: 4766670 (1988-08-01), Gazdik et al.
patent: 5304842 (1994-04-01), Farnworth et al.
patent: 5470787 (1995-11-01), Greer
patent: 5831445 (1998-11-01), Atkins et al.
patent: 5888850 (1999-03-01), Havens et al.
patent: 5897326 (1999-04-01), Eldridge et al.
patent: 5903058 (1999-05-01), Akram
patent: 6015722 (2000-01-01), Banks et al.
patent: 6091252 (2000-07-01), Akram et al.
patent: 6147374 (2000-11-01), Tanaka et al.
patent: 6211052 (2001-04-01), Farnworth
patent: 6219908 (2001-04-01), Farnworth et al.
patent: 6222280 (2001-04-01), Farnworth et al.
patent: 6248613 (2001-06-01), Matsuura et al.
patent: 6263566 (2001-07-01), Hembree et al.
patent: 6294270 (2001-09-01), Clough
patent: 6337577 (2002-01-01), Doherty et al.
patent: 6429113 (2002-08-01), Lewis et al.
Sony, “Sony Semiconductor Products Lead-free Package,” Sony Jul. 2000, 8 pages, <http://www.world.sony.com/semi/>.
National Semiconductor, “Semiconductor Packaging Assembly Technology,” 2000 National Semiconductor Corporation, Aug. 1999, 8 pages, www.national.com.
Kielin Erik J.
Micro)n Technology, Inc.
Perkins Coie LLP
Smoot Stephen W.
LandOfFree
Methods employing elevated temperatures to enhance quality... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods employing elevated temperatures to enhance quality..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods employing elevated temperatures to enhance quality... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3235189