Semiconductor device and method of manufacturing the same

Details Semiconductor device and method of manufacturing the same Semiconductor device and method of manufacturing the same

2001-03-27

2004-04-13

Baumeister, Bradley (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S751000, C257S759000, C257S760000, C438S638000

Reexamination Certificate

active

06720657

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the invention relates to a semiconductor device having improved wiring layers and a method of manufacturing the semiconductor device.
In recent years, large-scale integrated circuits (LSIs) are used in great numbers in the important sections of computers and communication apparatuses. An LSI is provided in the form of a single chip, incorporating many transistors, resistors and the like that are connected, forming electric circuits. The performance of a computer or communication apparatus largely depends on the performance of every LSI used. The performance of each LSI may be enhanced by increasing the integration density, or making the constituent elements smaller.
MOS transistors, for example, can be made small by reducing the gate length and the thickness of the source/drain diffusion layers.
To form thin source/drain diffusing layers, low-acceleration ion implantation is usually employed. This process can form source/drain diffusion layers that are as thin as 0.1 &mgr;m or less.
Here arises a problem. Any source/drain diffusion layer made by the low-acceleration ion implantation has a high sheet resistance of 100 ohms/square or more, though it is thin, serving to form small MOS transistors. Unless the sheet resistance of the layer is reduced, the LSI comprising the MOS transistors cannot operate at high speeds.
To manufacture a high-speed LSI such as a logic LSI, so-called silicide technique is employed. This technique consists in forming a silicide film, in self-alignment, on a source/drain diffusion layer and gate electrodes. (The gate electrodes have been made by processing a polycrystalline silicon film doped with impurities.)
In the manufacture of a dual-gate MOS transistor, the silicide technique can not only lower the resistance of the gate electrodes, but also decrease the number of manufacturing steps. Note that a dual-gate MOS transistor is composed of an n-channel MOS transistor and a p-channel MOS transistor, the former having a gate electrode made of polycrystalline silicon doped with n-type impurity, and the latter having a gate electrode made of polycrystalline silicon doped with p-type impurity.
The number of manufacturing steps can be decreased, because the gate electrodes (polycrystalline silicon strips) can be doped with impurities of a specific conductivity type in the step of forming the source/drain diffusion layer.
Dual-gate MOS transistors, each having polycide gate electrodes, are known. (A polycide gate electrode is composed of an impurity-doped polycrystalline silicon film and a metal silicide film, e.g., tungsten silicide film, formed on the impurity-doped polycrystalline silicon film.) In order to fabricate a dual-gate MOS transistor having polycide gate electrodes, a polycrystalline silicon film is masked with a metal silicide film during the ion implantation that is carried out to form a source/drain diffusion layer. Hence, the polycrystalline silicon film cannot be doped with impurities of a specific conductivity type.
It is therefore necessary to dope the polycrystalline silicon film with impurities of a specific conductivity type prior to the formation of the source/drain diffusion layer. Ions must be implanted to form the source/drain diffusion layer in one step, and ions must be implanted to dope the polycrystalline silicon film in another step. This increases the number of steps of manufacturing the dual-gate MOS transistor. More precisely, two more photolithography steps, two more ion implantation steps and two more resist-removing steps must be performed than in the case where the silicide technique is employed.
Any device that has a high integration density, such as a memory LSI (e.g., DRAM) must be of SAC (Self-Aligned Contact) structure. To provide a SAC structure, the inter-layer insulating film on a source/drain diffusion layer (usually, the one that is used as the source of a MOS transistor) is etched by RIE (Reactive Ion Etching), making a contact hole that extends to the source/drain diffusion layer. The contact hole may deviate from the desired position, but not so much as to expose the gate electrode (polycrystalline silicon film). To prevent the contact hole to deviate excessively from the desired position, a silicon nitride film, or an etching-stopping film, is formed on the gate electrode before the step of etching the inter-layer insulating film.
Due to the presence of the silicon nitride film, impurities cannot be injected into the gate electrode during the ion implantation for forming the source/drain diffusion layer. Hence, the silicide technique cannot be employed in the manufacture of memory LSIs, though it is applied in the manufacture of logic LSIs.
Most memory LSIs have gate electrodes made of polycrystalline silicon (i.e., polycrystalline silicon gate electrodes) that are doped with impurities. The polycrystalline silicon gate electrodes may be replaced by polysilycide gate electrodes, because the polysilicide gate electrodes have lower resistance. Alternatively, the polycrystalline silicon gate electrodes may be replaced by polymetal gate electrodes, each comprising a polycrystalline silicon film, a barrier metal film and a metal film (e.g., W film) laid one upon another in the order mentioned. Polymetal gate electrodes have lower resistance than the polysilicide gate electrodes and can therefore exhibit a sufficiently low resistance even if they are relatively thin. However, polymetal gate electrodes are disadvantageous in the following respect.
Logic LSIs have dual gates described above. Thus, if polymetal gate electrodes are used in a logic LSI, one step must be performed to implant impurity ions into the polycrystalline silicon film included in a polymetal gate electrode and another step must be carried out to implant impurity ions into the silicon substrate to form a source/drain diffusion layer, just as in the case where polysilicide gate electrodes are used in the logic LSI. This means an increase in the number of manufacturing steps, which inevitably raises the manufacturing cost.
In a hybrid LSI comprising logic ICs and a DRAM, a silicide film may be formed on the source/drain diffusion layers provided in the DRAM. If so, the leakage current at the pn-junctions of the memory cell increase, deteriorating the data-storing property of the DRAM. Additionally, the DRAM needs to have SAC structure as is described above. Hence, polycide electrodes made of tungsten (W) are used in the DRAM.
In a logic LSI, the MOS transistors need to have a low threshold voltage so that a current as large as possible may flow in the MOS transistors at low voltages. To this end, the gate electrode (i.e., polycrystalline silicon film) of each n-channel MOS transistor must be doped with n-type impurity such as P or As, thereby to have n
−
conductivity type, and the gate electrode of each p-channel MOS transistor must be doped with p-type impurity such as BF
2
, thereby to have p
+
conductivity type.
The performance of an LSI cannot be enhanced only if the resistances of the drain and source of each MOS transistor are lowered. To enhance the performance, it is also important to reduce parasitic resistance resulting from the wiring and increase the density of the wiring.
In a device such as a DRAM, in which wirings must be arranged at high density, it is important to form contacts on the wirings in self-alignment. How contacts are formed in self-alignment by a conventional method will be described, with reference to
FIGS. 4A
to
4
C, which are sectional views. The left half and right half of each figure show two regions of a device, respectively. The first region has a contact hole and a dual damascene (DD) wiring that has a width greater than the diameter of a contact hole. The second region has a contact hole and a DD wiring that has a width equal to the diameter of the contact hole.
As shown in
FIG. 4A
, DD wirings
83
made of W are formed. The DD wirings
83
electrically cont

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