Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
1999-07-08
2004-05-25
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S774000, C257S296000
Reexamination Certificate
active
06740979
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a defect analyzing LSI having memory cells, which is used for periodic monitoring in factories.
Semiconductor products are manufactured through a manufacturing line comprising a series of steps of process, but, for some cause or other in connection with the manufacture, defective semiconductor products are manufactured in some cases. In such a case, it is necessary to clear up the cause for the defect and improve a portion of the process to thereby eliminate the cause for the defect (process feedback) and thus to enhance the manufacturing yield of the semiconductor products. However, in order to analyze the defective semiconductor products and clear up the cause for the defect, very difficult work must be carried out.
Thus, for the purpose of enhancing the manufacturing yield of semiconductor products, there is periodically manufactured an LSI for defect analysis by the use of the semiconductor product manufacturing line. Defect analyzing LSIs are manufactured in a predetermined number without stopping the semiconductor product manufacturing line.
The defect analyzing LSI is specially manufactured solely for defect analysis, so that the structure thereof is simple. Thus, in case a defect has taken place in the semiconductor products manufactured, this defect analyzing LSI is analyzed, whereby the specifying of the defective portion in which a defect has taken place and the clearing-up of the cause for the defect, etc. become easier as compared with the case where the actual semiconductor products are analyzed.
By the way, as the defect analyzing LSI, there is known the type which is constituted in such a manner that, shown in FIG.
19
and
FIG. 20
, memory cell arrays (such as SRAM cell array)
11
are formed on a chip or on the chip area of a wafer. In case of a defect analyzing LSI which has memory cell arrays, the specifying of a defective portion and the clearing-up of the cause for the defect can be more easily carried out by utilizing the so-called FBM (Fail Bit Map) system.
The FBM system mentioned here is a system constituted in such a manner that the positions of the respective memory cells in a memory cell array are represented in the form of meshes, and all the memory cells are tested, so that the position of a defective memory cell is shown in the map, whereby the specifying of the defective portion and the clearing-up of the cause for the defect are made on the basis of the disposition (category) of the defective memory cell.
The wiring structure of the defect analyzing LSI is contrived in such a manner that the disposition (categories) of defective memory cells and the defective locations or the causes for the defects correspond to each other at a rate of one to one.
Table 1 shows the relationship between the categories and the defective locations or the causes for the defects in case defect analysis is made of the defect analyzing LSI shown in FIG.
19
and FIG.
20
.
TABLE 1
Category
Layer
Node 1
Node 2
o/s
1
Not applicable
Polycrystalline
Word line
—
open
silicone
2
Not applicable
Contact plug
Word line
—
open
(Poly-1Al)
3
Single-bit
Contact plug
Internal
—
open
defect
(SDG area)
wiring
3
Single-bit
Contact plug
Internal
—
open
defect
(Poly-1Al)
wiring
3
Single-bit
Polycrystalline
Internal
Internal
short
defect
silicone
wiring
wiring
Poly: polysilicon
Al: alminum
The “category” mentioned here means the disposition (pattern) of the defective memory cells detected by the defect analysis. The “layer” means the layer in which a defect has taken place, “Node
1
” and “Node
2
” each mean the wiring in which a defect has taken place; both the “layer” and “Node
1
,
2
” both specify the defective locations. The “o/s” means disconnection (open) or short-circuit (short), which specify the cause for a defect.
For example, (1) the disconnection of a word line (polycrystalline silicon layer) and (2) the disconnection of a contact plug (tungsten layer) which connects together a word line (polycrystalline layer) and a word line (first metal layer) correspond, respectively, to the disconnection of the polycrystalline silicon layer and the disconnection of a contact plug, which connects the polycrystalline silicon layer and the first metal layer to each other, in an actual semiconductor product (a logic circuit, a memory circuit or the like). However, even if the conventional defect analyzing LSI is analyzed by the use of the FBM system, these defects (disconnections) are not expressed in the form of categories.
More specifically, as shown in
FIG. 21
, in case of the conventional defect analyzing LSI structure, word lines (polycrystalline silicon layer)
12
and a word line (first metal layer)
13
lying above the word lines
12
both extend straight in the same direction, and they are both connected to each other at a plurality of locations by means of contact plugs
14
. Further, a signal is inputted through one end of the word line (first metal layer)
13
, and the other ends of the word lines (polycrystalline silicon layer, first metal layer)
12
,
13
are dead ends, which are not connected to anything. Further, between the two contact plugs
14
adjacent to each other, 8 (bits) memory cells are connected to the word line (polycrystalline silicon layer)
12
.
Thus, the memory cells are operated by the signal which propagates from the word line (first metal layer)
13
to the word lines (polycrystalline silicon layer)
12
via the contact plugs
14
. Here, even if a disconnection has taken place in, e.g., the word lines (polycrystalline silicon layer)
12
or in the contact plugs
14
, the memory cells operate without any trouble since the word lines (polycrystalline silicon layer)
12
and the word line (first metal layer)
13
are connected to each other by the plurality of contact plugs
14
.
That is, as shown in
FIG. 22
, no category appears on the FBM, and thus, the disconnection in the word lines (polycrystalline silicon layer) and the disconnection in the contact plugs cannot be detected.
Further, in case of using a defect analyzing LSI having SRAM cell arrays (hereinafter referred to as a SRAM-TEG (Test Element Group)), the memory cells of the SRAM-TEG correspond to the memory cells formed in an actual semiconductor product (a logic circuit, a memory circuit or the like).
However, even if the conventional SRAM-TEG is analyzed by the use of the FBM system, (3) the disconnection of the contact plugs with respect to the active area (SDG area) of the SRAM cells, the disconnection of the contact plugs with respect to the polycrystalline silicon layer within the SRAM cells, and the short-circuit of the polycrystalline silicon layer within the SRAM cells all come out as belonging to utterly the same category (single-bit defect), so that these defects cannot be distinguished from one another.
More specifically, in case of the conventional SRAM-TEG structure, the respective SRAM cell (1 bit) is comprised of four MOS transistors T
1
to T
4
and two transfer transistors T
5
, T
6
as shown in
FIGS. 23
to
25
. In FIG.
23
and
FIG. 24
, the transfer transistors T
5
, T
6
are omitted. Further, in
FIG. 24
, the hatched portions are composed of, for example, a metal layer 1Al.
Here, the disconnection of a contact plug with respect to the active area (SDG area) of the SRAM cell, the disconnection of a contact plug with respect to the polycrystalline silicon layer within the SRAM cell, and the short-circuit of the polycrystalline silicon layer within the SRAM cell all result in disabling only one SRAM cell.
That is, even if any of the above-mentioned three types of defects has taken place, merely the category of “single-bit defect” appears on the FBM as shown in FIG.
26
.
As stated above, conventionally, a defect analyzing LSI is periodically manufactured separately from semiconductor products to make defect analysis on the basis of this defect analyzing LSI, but, in case of the conventional defect analyzing LSI, there is the drawback that a defect cannot be detected, or a plurality of different defects appea
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Rose Kiesha
Zarabian Amir
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