Image analysis – Image transformation or preprocessing – Changing the image coordinates
Reexamination Certificate
1999-03-09
2004-03-23
Grant, II, Jerome (Department: 2722)
Image analysis
Image transformation or preprocessing
Changing the image coordinates
C348S441000
Reexamination Certificate
active
06711305
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an image processing apparatus and method for decoding coded image data.
2. Description of the Related Art
FIG. 1
is a block diagram showing a conventional image decoding apparatus for decoding image data that has been compressed and coded.
In
FIG. 1
, a CPU
2
reads image data that has been compressed and coded using, for example the Joint Photographic Coding Experts Group (JPEG) method and recorded on a flash memory card
1
. The image data is temporarily stored in a memory
3
. The coded data stored in the memory
3
is decoded by a JPEG decoding circuit
4
. At this time, the decoded image data is output from the JPEG decoding circuit
4
in units of a block composed of 64 pixels arranged in a matrix of 8 pixels in a row by 8 pixels in a column. Each pixel represents a luminance level (hereinafter Y) and chrominance levels (hereinafter U and V).
Block data of each color component (Y, U, or V) output from the JPEG decoding circuit
4
is converted into Y, U, or V data, by a raster block conversion circuit
5
. The Y, U, or V data is formatted suitably for raster scan.
The converted image data is held in a first-in first-out (FIFO) VRAM
6
which holds an amount needed to render one screen. The FIFO VRAM
6
outputs input information data in FIFO sequence. In the case of inputting data formatted in the sequence of scanning lines constituting a raster, inputting is repeated in that sequence. The formatting is therefore suitable for outputting data to an LCD, TV, or the like. Moreover, a sync signal generator (SSG)
13
in
FIG. 1
generates a timing signal such as a sync signal employed in television.
The FIFO VRAM
6
outputs image data synchronously with the television sync signal generated by the SSG
13
. When image data rendering a first field is output from the FIFO VRAM
6
, a selection switch
9
is connected to a terminal “b”. The image data is sent to an encoder
10
as it is.
The encoder
10
modulates in amplitude the U and V data items according to a sub carrier, and adds the data items to the Y data. The encoder
10
then adds the sync signal to the resultant data. The image data encoded by the encoder
10
is converted into an analog image signal by a D/A converter
11
. An image is then displayed on a display device
12
such as an LCD or CRT according to the image data.
Next, when image data rendering a second field is output from the FIFO VRAM
6
, the selection switch
9
is connected to a terminal “a”. A signal output from the FIFO VRAM
6
in response to a signal FI, and a signal produced by delaying the output signal by 1H (a horizontal scanning period) by a delay circuit
7
are averaged by an averaging circuit
8
. A resultant signal is then output to the encoder
10
.
Assume that the foregoing image decoding apparatus attempts to decode image data arranged in a matrix of 640 pixels in a row and 480 pixels in a column. Image data formatted in units of a block and decoded by the JPEG decoding circuit
4
is converted into data formatted suitably for raster scan. At this time, a storage capacity of a product of 640 pixels by 8 lines is necessary. Moreover, two memories having the storage capacity of a product of 640 pixels by 8 lines are prepared for pipelining the conversion. Thus, writing and reading are generally carried out simultaneously.
The FIFO VRAM
6
is expensive. The FIFO VRAM
6
is therefore often designed to offer a storage capacity permitting accumulation of data representing a product of 640 by 240 dots. In this case, as mentioned above, the switch
9
must be designed to be able to be changed over to the delay circuit
7
or averaging circuit
7
field by field. In this case, interlacing must be adopted.
If the FIFO VRAM
6
were designed to offer a storage capacity equivalent to a product of 640 by 480 dots, the delay circuit
7
would be unnecessary. However, this poses a problem in that the FIFO VRAM
6
becomes more expensive along with the increase in capacity.
Moreover, if the FIFO VRAM
6
were designed to offer a storage capacity equivalent to a product of 640 by 240 dots, and the delay circuit
7
were excluded, a TV image would swing lengthwise.
SUMMARY OF THE INVENTION
In consideration of the aforesaid background, one object of the present invention is to provide an image processing apparatus and method in which the number of memories is decreased to accomplish a reduction in cost without deterioration of image reproducibility.
Accordingly, in one preferred embodiment, an image processing apparatus and method are characterized in that image data is input in units of a block composed of a plurality of pixels. The input image data is stored in a memory; access addresses used to access the memory are controlled to convert the image data into image data formatted in the sequence of scanning lines constituting a raster. Interpolated image data is produced using the converted image data, which has been delayed in the memory used for the conversion, and the converted image data that has not been delayed.
Moreover, in one preferred embodiment, an image processing apparatus and method are characterized in that: image data is input in the sequence of scanning lines constituting a raster. The input image data is stored in a memory and access addresses used to access the memory are controlled to convert the image data into image data formatted in the sequence of blocks. Interpolated image data is produced using the image data that has been delayed in the memory used for conversion, and the image data that has not been delayed.
Other objects, features and advantages of the invention will become apparent from the following detailed description taken into conjunction with the accompanying drawings.
REFERENCES:
patent: 4298867 (1981-11-01), Craig
patent: 5459519 (1995-10-01), Scalise et al.
patent: 6052159 (2000-04-01), Ishii et al.
patent: 0205554 (1990-12-01), None
patent: 0626788 (1994-11-01), None
patent: 8-18791 (1996-01-01), None
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