Semiconductor memory device with internal clock generation...

Details Semiconductor memory device with internal clock generation... Semiconductor memory device with internal clock generation...

2002-09-27

2004-07-27

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S193000, C365S194000, C365S189050

Reexamination Certificate

active

06768698

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device with an internal clock generation circuit operating in synchronization with a rise and a fall of an external clock and generating an internal clock synchronized with the external clock.
2. Description of the Background Art
Generally, an SDRAM (Synchronous Dynamic Random Access Memory) operating in synchronization with an external clock includes therein a clock generation circuit which generates an internal clock synchronized with the external clock. Using this internal clock, an internal circuit in SDRAM is controlled.
More specifically, a circuit controlling data input/output for SDRAM to communicate data with the outside is also controlled by this internal clock. Therefore, the timing of data input/output is largely affected by the phase accuracy of the internal clock.
Meanwhile, by the demand for a higher frequency operation of a semiconductor device, a DDR SDRAM (Double Data Rate SDRAM) is developed and brought into practical use, in which data is input/output in synchronization with rising and falling edges of an external clock. In this DDR SDRAM, it is particularly demanded to further reduce a phase difference between an edge of an external clock and data input/output timing for DDR SDRAM, as compared with a conventional SDRAM. Specifically, since DDR SDRAM allows data input and output at a frequency rate double the conventional SDRAM, the phase shift between the edge of the external clock and the data input/output timing is larger relative to the period of the external clock.
FIG. 12
is a timing chart showing data output timing in reading data from a DDR SDRAM, that is a so-called DDR-I. In this DDR SDRAM, a CAS latency CL is set at 2.5 and a burst length BL is set at 4. The CAS latency represents here the number of cycles (one cycle corresponds to the time period from a rise of an external clock EXTCLK to the next rise) for the DDR SDRAM to receive a READ command (a command for reading data) from the outside and then to start to output the read data to the outside. The burst length represents the number of bits successively read out in response to READ command.
Referring to
FIG. 12
, DDR-I outputs data DQ of the read data and a data strobe signal DQS in synchronization with external clocks EXTCLK, EXT/CLK. The external clock EXT/CLK here is a clock signal complementary to the external clock EXTCLK. The data strobe signal DQS is used as a timing to take in data DQ on the side of an external controller receiving data DQ.
A timing difference tAC between the edges of external clocks EXTCLK, EXT/CLK and the output of data DQ is defined to fall within a certain range. In
FIG. 12
, timing difference tAC is controlled to be zero. Furthermore, an output timing difference tDQSQ between data strobe signal DQS and data DQ also needs to fall within a certain range.
In addition, in DDR-I, data strobe signal DQS in reading data is defined to be generated (CAS latency CL-1) cycle before data DQ starts to be output. This period is called “preamble”. It is also defined that data strobe signal DQS is at L (logic low) level during half cycle after the final data of data DQ starts to be output. This period is called “postamble”.
In order to realize a data output as shown in
FIG. 12
, an operation clock is required of which timing is slightly earlier than that of the edge of external clock EXTCLK, in a data output circuit. This is because a delay is occurred before data is actually output after an external clock is input into a semiconductor memory device, because of a capacitance of each internal circuit.
More specifically, what is needed is a clock generation circuit operating in a manner as follows. As external clock EXTCLK is a fixed cycle signal, internal clocks CLK_P, CLK_N shifted backward by an adequate amount of time Ta with respect to the edge of external clock EXTCLK are generated by delaying external clock EXTCLK by an adequate amount of delay Td. Furthermore, delay amount Td can be controlled such that data DQ output from the data output circuit and data strobe signal DQS output from a data strobe signal output circuit, which operate triggered by these internal clocks CLK_P and CLK_N, satisfy the differences tAC and tDQSQ described above. A circuit that generates such an internal clock is called a DLL (Delay Locked Loop) circuit.
The backward amount Ta is determined from a propagation time from taking in the read data triggered by internal clocks CLK_P, CLK_N to ultimately reading out the read data to a data output terminal. Then, as shown in
FIG. 12
, when CAS latency is 2.5, the first data of data DQ is output in synchronization with the rising edge of EXT/CLK (the falling edge of EXTCLK), and thereafter odd numbered data and even numbered data of data DQ are sequentially output to the outside, respectively triggered by internal clocks CLK_N and CLK_P.
FIG. 13
is a schematic block diagram conceptually illustrating an overall configuration of an READ-related circuitry operating with an internal clock generated in the DLL circuit described above.
Referring to
FIG. 13
, a DLL circuit
100
outputs an internal clock CLK_PF generated by delaying external clock EXTCLK and an internal clock CLK_NF generated by delaying external clock EXT/CLK. A repeater
120
receives internal clocks CLK_PF and CLK_NF distributed from DLL circuit
100
and outputs them as DLL clocks CLK_P and CLK_N.
A plurality of data output circuits
200
are provided based on a word organization to which DDR SDRAM corresponds. Here, sixteen data output circuits
200
outputting data DQ
0
-DQ
15
are provided. Each data output circuit
200
receives DLL clocks CLK_P and CLK_N output from repeater
120
, is activated by either of DLL clock CLK_P or CLK_N selected based on an internal signal NZPCNT received from a READ control circuit
400
, and takes in and externally outputs data read from a memory cell array onto a data bus.
As shown in
FIG. 13
, a signal path from DLL circuit
100
to data output circuits
200
is generally formed like a tree. The circuits and signal lines are arranged such that the data output timings do not vary among a plurality of data output circuits
200
. A repeater
120
is generally arranged for every eight data output circuits or every four data output circuits.
A data strobe signal output circuit
500
generates and externally outputs data strobe signals LDQS and UDQS which indicate of timing for externally outputting the read data output from data output circuit
200
. Data strobe signal output circuit
500
receives DLL clocks CLK_P and CLK_N output from repeater
120
, generates data strobe signals LDQS and UDQS during the period from preamble to postamble using an internal signal QSOE received from READ control circuit
400
, in synchronization with DLL clocks CLK_P and CLK_N, and externally outputs the generated data strobe signals LDQS and UDQS.
READ control circuit
400
operates in synchronization with internal clocks CLK_PF and CLK_NF received from DLL circuit
100
, generates a variety of signals required for a data reading operation in response to READ command, and outputs the signals to data output circuit
200
and data strobe signal output circuit
500
. Internal signals QSOE, DOE, EZORG, RDETG and NZPCNT will be described later in the description of data output circuit
200
and data strobe signal output circuit
500
using these signals.
FIG. 14
is a functional block diagram illustrating DLL circuit
100
.
Referring to
FIG. 14
, DLL circuit
100
includes variable delay circuits
206
and
208
, pulse generation circuits
210
and
212
, an input/output replica circuit
214
, a phase comparator
216
and a delay control circuit
218
.
An input buffer
202
receiving external clocks EXTCLK and EXT/CLK input from the outside and outputting an internal clock BUFFCLK_DLL to DLL circuit
100
detects a cross point between a potential level in the rise of external clock EXTCLK and a potential l

Affiliated with

Also associated with

Rating

Semiconductor memory device with internal clock generation... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device with internal clock generation..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device with internal clock generation... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3232806